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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Jakub Jermar |
2 | * Copyright (c) 2006 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/mm/as.h> |
35 | #include <arch/mm/as.h> |
36 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
37 | #include <genarch/mm/page_ht.h> |
37 | #include <genarch/mm/page_ht.h> |
38 | #include <genarch/mm/asid_fifo.h> |
38 | #include <genarch/mm/asid_fifo.h> |
39 | #include <debug.h> |
39 | #include <debug.h> |
40 | #include <config.h> |
40 | #include <config.h> |
41 | 41 | ||
42 | #ifdef CONFIG_TSB |
42 | #ifdef CONFIG_TSB |
43 | #include <arch/mm/tsb.h> |
43 | #include <arch/mm/tsb.h> |
44 | #include <arch/memstr.h> |
44 | #include <arch/memstr.h> |
45 | #include <synch/mutex.h> |
45 | #include <synch/mutex.h> |
46 | #include <arch/asm.h> |
46 | #include <arch/asm.h> |
47 | #include <mm/frame.h> |
47 | #include <mm/frame.h> |
48 | #include <bitops.h> |
48 | #include <bitops.h> |
49 | #include <macros.h> |
49 | #include <macros.h> |
50 | #endif /* CONFIG_TSB */ |
50 | #endif /* CONFIG_TSB */ |
51 | 51 | ||
52 | /** Architecture dependent address space init. */ |
52 | /** Architecture dependent address space init. */ |
53 | void as_arch_init(void) |
53 | void as_arch_init(void) |
54 | { |
54 | { |
55 | if (config.cpu_active == 1) { |
55 | if (config.cpu_active == 1) { |
56 | as_operations = &as_ht_operations; |
56 | as_operations = &as_ht_operations; |
57 | asid_fifo_init(); |
57 | asid_fifo_init(); |
58 | } |
58 | } |
59 | } |
59 | } |
60 | 60 | ||
61 | int as_constructor_arch(as_t *as, int flags) |
61 | int as_constructor_arch(as_t *as, int flags) |
62 | { |
62 | { |
63 | #ifdef CONFIG_TSB |
63 | #ifdef CONFIG_TSB |
- | 64 | /* |
|
- | 65 | * The order must be calculated with respect to the emulated |
|
- | 66 | * 16K page size. |
|
- | 67 | */ |
|
64 | int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
68 | int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
65 | sizeof(tsb_entry_t)) >> MMU_FRAME_WIDTH); |
69 | sizeof(tsb_entry_t)) >> FRAME_WIDTH); |
66 | uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
70 | uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
67 | 71 | ||
68 | if (!tsb) |
72 | if (!tsb) |
69 | return -1; |
73 | return -1; |
70 | 74 | ||
71 | as->arch.itsb = (tsb_entry_t *) tsb; |
75 | as->arch.itsb = (tsb_entry_t *) tsb; |
72 | as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * |
76 | as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * |
73 | sizeof(tsb_entry_t)); |
77 | sizeof(tsb_entry_t)); |
74 | memsetb((uintptr_t) as->arch.itsb, |
78 | memsetb((uintptr_t) as->arch.itsb, |
75 | (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); |
79 | (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); |
76 | #endif |
80 | #endif |
77 | return 0; |
81 | return 0; |
78 | } |
82 | } |
79 | 83 | ||
80 | int as_destructor_arch(as_t *as) |
84 | int as_destructor_arch(as_t *as) |
81 | { |
85 | { |
82 | #ifdef CONFIG_TSB |
86 | #ifdef CONFIG_TSB |
- | 87 | /* |
|
- | 88 | * The count must be calculated with respect to the emualted 16K page |
|
- | 89 | * size. |
|
- | 90 | */ |
|
83 | count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
91 | count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
84 | sizeof(tsb_entry_t)) >> MMU_FRAME_WIDTH; |
92 | sizeof(tsb_entry_t)) >> FRAME_WIDTH; |
85 | frame_free(KA2PA((uintptr_t) as->arch.itsb)); |
93 | frame_free(KA2PA((uintptr_t) as->arch.itsb)); |
86 | return cnt; |
94 | return cnt; |
87 | #else |
95 | #else |
88 | return 0; |
96 | return 0; |
89 | #endif |
97 | #endif |
90 | } |
98 | } |
91 | 99 | ||
92 | int as_create_arch(as_t *as, int flags) |
100 | int as_create_arch(as_t *as, int flags) |
93 | { |
101 | { |
94 | #ifdef CONFIG_TSB |
102 | #ifdef CONFIG_TSB |
95 | ipl_t ipl; |
103 | ipl_t ipl; |
96 | 104 | ||
97 | ipl = interrupts_disable(); |
105 | ipl = interrupts_disable(); |
98 | mutex_lock_active(&as->lock); /* completely unnecessary, but polite */ |
106 | mutex_lock_active(&as->lock); /* completely unnecessary, but polite */ |
99 | tsb_invalidate(as, 0, (count_t) -1); |
107 | tsb_invalidate(as, 0, (count_t) -1); |
100 | mutex_unlock(&as->lock); |
108 | mutex_unlock(&as->lock); |
101 | interrupts_restore(ipl); |
109 | interrupts_restore(ipl); |
102 | #endif |
110 | #endif |
103 | return 0; |
111 | return 0; |
104 | } |
112 | } |
105 | 113 | ||
106 | /** Perform sparc64-specific tasks when an address space becomes active on the |
114 | /** Perform sparc64-specific tasks when an address space becomes active on the |
107 | * processor. |
115 | * processor. |
108 | * |
116 | * |
109 | * Install ASID and map TSBs. |
117 | * Install ASID and map TSBs. |
110 | * |
118 | * |
111 | * @param as Address space. |
119 | * @param as Address space. |
112 | */ |
120 | */ |
113 | void as_install_arch(as_t *as) |
121 | void as_install_arch(as_t *as) |
114 | { |
122 | { |
115 | tlb_context_reg_t ctx; |
123 | tlb_context_reg_t ctx; |
116 | 124 | ||
117 | /* |
125 | /* |
118 | * Note that we don't lock the address space. |
126 | * Note that we don't lock the address space. |
119 | * That's correct - we can afford it here |
127 | * That's correct - we can afford it here |
120 | * because we only read members that are |
128 | * because we only read members that are |
121 | * currently read-only. |
129 | * currently read-only. |
122 | */ |
130 | */ |
123 | 131 | ||
124 | /* |
132 | /* |
125 | * Write ASID to secondary context register. |
133 | * Write ASID to secondary context register. |
126 | * The primary context register has to be set |
134 | * The primary context register has to be set |
127 | * from TL>0 so it will be filled from the |
135 | * from TL>0 so it will be filled from the |
128 | * secondary context register from the TL=1 |
136 | * secondary context register from the TL=1 |
129 | * code just before switch to userspace. |
137 | * code just before switch to userspace. |
130 | */ |
138 | */ |
131 | ctx.v = 0; |
139 | ctx.v = 0; |
132 | ctx.context = as->asid; |
140 | ctx.context = as->asid; |
133 | mmu_secondary_context_write(ctx.v); |
141 | mmu_secondary_context_write(ctx.v); |
134 | 142 | ||
135 | #ifdef CONFIG_TSB |
143 | #ifdef CONFIG_TSB |
136 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
144 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
137 | 145 | ||
138 | ASSERT(as->arch.itsb && as->arch.dtsb); |
146 | ASSERT(as->arch.itsb && as->arch.dtsb); |
139 | 147 | ||
140 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
148 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
141 | 149 | ||
142 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
150 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
143 | /* |
151 | /* |
144 | * TSBs were allocated from memory not covered |
152 | * TSBs were allocated from memory not covered |
145 | * by the locked 4M kernel DTLB entry. We need |
153 | * by the locked 4M kernel DTLB entry. We need |
146 | * to map both TSBs explicitly. |
154 | * to map both TSBs explicitly. |
147 | */ |
155 | */ |
148 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
156 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
149 | dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); |
157 | dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); |
150 | } |
158 | } |
151 | 159 | ||
152 | /* |
160 | /* |
153 | * Setup TSB Base registers. |
161 | * Setup TSB Base registers. |
154 | */ |
162 | */ |
155 | tsb_base_reg_t tsb_base; |
163 | tsb_base_reg_t tsb_base; |
156 | 164 | ||
157 | tsb_base.value = 0; |
165 | tsb_base.value = 0; |
158 | tsb_base.size = TSB_SIZE; |
166 | tsb_base.size = TSB_SIZE; |
159 | tsb_base.split = 0; |
167 | tsb_base.split = 0; |
160 | 168 | ||
161 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; |
169 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; |
162 | itsb_base_write(tsb_base.value); |
170 | itsb_base_write(tsb_base.value); |
163 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH; |
171 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH; |
164 | dtsb_base_write(tsb_base.value); |
172 | dtsb_base_write(tsb_base.value); |
165 | #endif |
173 | #endif |
166 | } |
174 | } |
167 | 175 | ||
168 | /** Perform sparc64-specific tasks when an address space is removed from the |
176 | /** Perform sparc64-specific tasks when an address space is removed from the |
169 | * processor. |
177 | * processor. |
170 | * |
178 | * |
171 | * Demap TSBs. |
179 | * Demap TSBs. |
172 | * |
180 | * |
173 | * @param as Address space. |
181 | * @param as Address space. |
174 | */ |
182 | */ |
175 | void as_deinstall_arch(as_t *as) |
183 | void as_deinstall_arch(as_t *as) |
176 | { |
184 | { |
177 | 185 | ||
178 | /* |
186 | /* |
179 | * Note that we don't lock the address space. |
187 | * Note that we don't lock the address space. |
180 | * That's correct - we can afford it here |
188 | * That's correct - we can afford it here |
181 | * because we only read members that are |
189 | * because we only read members that are |
182 | * currently read-only. |
190 | * currently read-only. |
183 | */ |
191 | */ |
184 | 192 | ||
185 | #ifdef CONFIG_TSB |
193 | #ifdef CONFIG_TSB |
186 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
194 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
187 | 195 | ||
188 | ASSERT(as->arch.itsb && as->arch.dtsb); |
196 | ASSERT(as->arch.itsb && as->arch.dtsb); |
189 | 197 | ||
190 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
198 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
191 | 199 | ||
192 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
200 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
193 | /* |
201 | /* |
194 | * TSBs were allocated from memory not covered |
202 | * TSBs were allocated from memory not covered |
195 | * by the locked 4M kernel DTLB entry. We need |
203 | * by the locked 4M kernel DTLB entry. We need |
196 | * to demap the entry installed by as_install_arch(). |
204 | * to demap the entry installed by as_install_arch(). |
197 | */ |
205 | */ |
198 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
206 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
199 | } |
207 | } |
200 | #endif |
208 | #endif |
201 | } |
209 | } |
202 | 210 | ||
203 | /** @} |
211 | /** @} |
204 | */ |
212 | */ |
205 | 213 |