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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * @brief Exception handlers and exception initialization routines. |
33 | * @brief Exception handlers and exception initialization routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <arch/exception.h> |
36 | #include <arch/exception.h> |
37 | #include <arch/debug/print.h> |
- | |
38 | #include <arch/memstr.h> |
37 | #include <arch/memstr.h> |
39 | #include <arch/regutils.h> |
38 | #include <arch/regutils.h> |
40 | #include <interrupt.h> |
39 | #include <interrupt.h> |
41 | #include <arch/machine.h> |
- | |
42 | #include <arch/mm/page_fault.h> |
40 | #include <arch/mm/page_fault.h> |
43 | #include <arch/barrier.h> |
41 | #include <arch/barrier.h> |
- | 42 | #include <arch/drivers/gxemul.h> |
|
44 | #include <print.h> |
43 | #include <print.h> |
45 | #include <syscall/syscall.h> |
44 | #include <syscall/syscall.h> |
46 | 45 | ||
47 | /** Offset used in calculation of exception handler's relative address. |
46 | /** Offset used in calculation of exception handler's relative address. |
48 | * |
47 | * |
49 | * @see install_handler() |
48 | * @see install_handler() |
50 | */ |
49 | */ |
51 | #define PREFETCH_OFFSET 0x8 |
50 | #define PREFETCH_OFFSET 0x8 |
52 | 51 | ||
53 | /** LDR instruction's code */ |
52 | /** LDR instruction's code */ |
54 | #define LDR_OPCODE 0xe59ff000 |
53 | #define LDR_OPCODE 0xe59ff000 |
55 | 54 | ||
56 | /** Number of exception vectors. */ |
55 | /** Number of exception vectors. */ |
57 | #define EXC_VECTORS 8 |
56 | #define EXC_VECTORS 8 |
58 | 57 | ||
59 | /** Size of memory block occupied by exception vectors. */ |
58 | /** Size of memory block occupied by exception vectors. */ |
60 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
59 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
61 | 60 | ||
62 | /** Switches to kernel stack and saves all registers there. |
61 | /** Switches to kernel stack and saves all registers there. |
63 | * |
62 | * |
64 | * Temporary exception stack is used to save a few registers |
63 | * Temporary exception stack is used to save a few registers |
65 | * before stack switch takes place. |
64 | * before stack switch takes place. |
66 | * |
65 | * |
67 | */ |
66 | */ |
68 | inline static void setup_stack_and_save_regs() |
67 | inline static void setup_stack_and_save_regs() |
69 | { |
68 | { |
70 | asm volatile ( |
69 | asm volatile ( |
71 | "ldr r13, =exc_stack\n" |
70 | "ldr r13, =exc_stack\n" |
72 | "stmfd r13!, {r0}\n" |
71 | "stmfd r13!, {r0}\n" |
73 | "mrs r0, spsr\n" |
72 | "mrs r0, spsr\n" |
74 | "and r0, r0, #0x1f\n" |
73 | "and r0, r0, #0x1f\n" |
75 | "cmp r0, #0x10\n" |
74 | "cmp r0, #0x10\n" |
76 | "bne 1f\n" |
75 | "bne 1f\n" |
77 | 76 | ||
78 | /* prev mode was usermode */ |
77 | /* prev mode was usermode */ |
79 | "ldmfd r13!, {r0}\n" |
78 | "ldmfd r13!, {r0}\n" |
80 | "ldr r13, =supervisor_sp\n" |
79 | "ldr r13, =supervisor_sp\n" |
81 | "ldr r13, [r13]\n" |
80 | "ldr r13, [r13]\n" |
82 | "stmfd r13!, {lr}\n" |
81 | "stmfd r13!, {lr}\n" |
83 | "stmfd r13!, {r0-r12}\n" |
82 | "stmfd r13!, {r0-r12}\n" |
84 | "stmfd r13!, {r13, lr}^\n" |
83 | "stmfd r13!, {r13, lr}^\n" |
85 | "mrs r0, spsr\n" |
84 | "mrs r0, spsr\n" |
86 | "stmfd r13!, {r0}\n" |
85 | "stmfd r13!, {r0}\n" |
87 | "b 2f\n" |
86 | "b 2f\n" |
88 | 87 | ||
89 | /* mode was not usermode */ |
88 | /* mode was not usermode */ |
90 | "1:\n" |
89 | "1:\n" |
91 | "stmfd r13!, {r1, r2, r3}\n" |
90 | "stmfd r13!, {r1, r2, r3}\n" |
92 | "mrs r1, cpsr\n" |
91 | "mrs r1, cpsr\n" |
93 | "mov r2, lr\n" |
92 | "mov r2, lr\n" |
94 | "bic r1, r1, #0x1f\n" |
93 | "bic r1, r1, #0x1f\n" |
95 | "orr r1, r1, r0\n" |
94 | "orr r1, r1, r0\n" |
96 | "mrs r0, cpsr\n" |
95 | "mrs r0, cpsr\n" |
97 | "msr cpsr_c, r1\n" |
96 | "msr cpsr_c, r1\n" |
98 | 97 | ||
99 | "mov r3, r13\n" |
98 | "mov r3, r13\n" |
100 | "stmfd r13!, {r2}\n" |
99 | "stmfd r13!, {r2}\n" |
101 | "mov r2, lr\n" |
100 | "mov r2, lr\n" |
102 | "stmfd r13!, {r4-r12}\n" |
101 | "stmfd r13!, {r4-r12}\n" |
103 | "mov r1, r13\n" |
102 | "mov r1, r13\n" |
104 | 103 | ||
105 | /* the following two lines are for debugging */ |
104 | /* the following two lines are for debugging */ |
106 | "mov sp, #0\n" |
105 | "mov sp, #0\n" |
107 | "mov lr, #0\n" |
106 | "mov lr, #0\n" |
108 | "msr cpsr_c, r0\n" |
107 | "msr cpsr_c, r0\n" |
109 | 108 | ||
110 | "ldmfd r13!, {r4, r5, r6, r7}\n" |
109 | "ldmfd r13!, {r4, r5, r6, r7}\n" |
111 | "stmfd r1!, {r4, r5, r6}\n" |
110 | "stmfd r1!, {r4, r5, r6}\n" |
112 | "stmfd r1!, {r7}\n" |
111 | "stmfd r1!, {r7}\n" |
113 | "stmfd r1!, {r2}\n" |
112 | "stmfd r1!, {r2}\n" |
114 | "stmfd r1!, {r3}\n" |
113 | "stmfd r1!, {r3}\n" |
115 | "mrs r0, spsr\n" |
114 | "mrs r0, spsr\n" |
116 | "stmfd r1!, {r0}\n" |
115 | "stmfd r1!, {r0}\n" |
117 | "mov r13, r1\n" |
116 | "mov r13, r1\n" |
118 | 117 | ||
119 | "2:\n" |
118 | "2:\n" |
120 | ); |
119 | ); |
121 | } |
120 | } |
122 | 121 | ||
123 | /** Returns from exception mode. |
122 | /** Returns from exception mode. |
124 | * |
123 | * |
125 | * Previously saved state of registers (including control register) |
124 | * Previously saved state of registers (including control register) |
126 | * is restored from the stack. |
125 | * is restored from the stack. |
127 | */ |
126 | */ |
128 | inline static void load_regs() |
127 | inline static void load_regs() |
129 | { |
128 | { |
130 | asm volatile( |
129 | asm volatile( |
131 | "ldmfd r13!, {r0} \n" |
130 | "ldmfd r13!, {r0} \n" |
132 | "msr spsr, r0 \n" |
131 | "msr spsr, r0 \n" |
133 | "and r0, r0, #0x1f \n" |
132 | "and r0, r0, #0x1f \n" |
134 | "cmp r0, #0x10 \n" |
133 | "cmp r0, #0x10 \n" |
135 | "bne 1f \n" |
134 | "bne 1f \n" |
136 | 135 | ||
137 | /* return to user mode */ |
136 | /* return to user mode */ |
138 | "ldmfd r13!, {r13, lr}^ \n" |
137 | "ldmfd r13!, {r13, lr}^ \n" |
139 | "b 2f \n" |
138 | "b 2f \n" |
140 | 139 | ||
141 | /* return to non-user mode */ |
140 | /* return to non-user mode */ |
142 | "1:\n" |
141 | "1:\n" |
143 | "ldmfd r13!, {r1, r2} \n" |
142 | "ldmfd r13!, {r1, r2} \n" |
144 | "mrs r3, cpsr \n" |
143 | "mrs r3, cpsr \n" |
145 | "bic r3, r3, #0x1f \n" |
144 | "bic r3, r3, #0x1f \n" |
146 | "orr r3, r3, r0 \n" |
145 | "orr r3, r3, r0 \n" |
147 | "mrs r0, cpsr \n" |
146 | "mrs r0, cpsr \n" |
148 | "msr cpsr_c, r3 \n" |
147 | "msr cpsr_c, r3 \n" |
149 | 148 | ||
150 | "mov r13, r1 \n" |
149 | "mov r13, r1 \n" |
151 | "mov lr, r2 \n" |
150 | "mov lr, r2 \n" |
152 | "msr cpsr_c, r0 \n" |
151 | "msr cpsr_c, r0 \n" |
153 | 152 | ||
154 | /* actual return */ |
153 | /* actual return */ |
155 | "2:\n" |
154 | "2:\n" |
156 | "ldmfd r13, {r0-r12, pc}^\n" |
155 | "ldmfd r13, {r0-r12, pc}^\n" |
157 | ); |
156 | ); |
158 | } |
157 | } |
159 | 158 | ||
160 | 159 | ||
161 | /** Switch CPU to mode in which interrupts are serviced (currently it |
160 | /** Switch CPU to mode in which interrupts are serviced (currently it |
162 | * is Undefined mode). |
161 | * is Undefined mode). |
163 | * |
162 | * |
164 | * The default mode for interrupt servicing (Interrupt Mode) |
163 | * The default mode for interrupt servicing (Interrupt Mode) |
165 | * can not be used because of nested interrupts (which can occur |
164 | * can not be used because of nested interrupts (which can occur |
166 | * because interrupts are enabled in higher levels of interrupt handler). |
165 | * because interrupts are enabled in higher levels of interrupt handler). |
167 | */ |
166 | */ |
168 | inline static void switch_to_irq_servicing_mode() |
167 | inline static void switch_to_irq_servicing_mode() |
169 | { |
168 | { |
170 | /* switch to Undefined mode */ |
169 | /* switch to Undefined mode */ |
171 | asm volatile( |
170 | asm volatile( |
172 | /* save regs used during switching */ |
171 | /* save regs used during switching */ |
173 | "stmfd sp!, {r0-r3} \n" |
172 | "stmfd sp!, {r0-r3} \n" |
174 | 173 | ||
175 | /* save stack pointer and link register to r1, r2 */ |
174 | /* save stack pointer and link register to r1, r2 */ |
176 | "mov r1, sp \n" |
175 | "mov r1, sp \n" |
177 | "mov r2, lr \n" |
176 | "mov r2, lr \n" |
178 | 177 | ||
179 | /* mode switch */ |
178 | /* mode switch */ |
180 | "mrs r0, cpsr \n" |
179 | "mrs r0, cpsr \n" |
181 | "bic r0, r0, #0x1f \n" |
180 | "bic r0, r0, #0x1f \n" |
182 | "orr r0, r0, #0x1b \n" |
181 | "orr r0, r0, #0x1b \n" |
183 | "msr cpsr_c, r0 \n" |
182 | "msr cpsr_c, r0 \n" |
184 | 183 | ||
185 | /* restore saved sp and lr */ |
184 | /* restore saved sp and lr */ |
186 | "mov sp, r1 \n" |
185 | "mov sp, r1 \n" |
187 | "mov lr, r2 \n" |
186 | "mov lr, r2 \n" |
188 | 187 | ||
189 | /* restore original regs */ |
188 | /* restore original regs */ |
190 | "ldmfd sp!, {r0-r3} \n" |
189 | "ldmfd sp!, {r0-r3} \n" |
191 | ); |
190 | ); |
192 | } |
191 | } |
193 | 192 | ||
194 | /** Calls exception dispatch routine. */ |
193 | /** Calls exception dispatch routine. */ |
195 | #define CALL_EXC_DISPATCH(exception) \ |
194 | #define CALL_EXC_DISPATCH(exception) \ |
196 | asm volatile ( \ |
195 | asm volatile ( \ |
197 | "mov r0, %[exc]\n" \ |
196 | "mov r0, %[exc]\n" \ |
198 | "mov r1, r13\n" \ |
197 | "mov r1, r13\n" \ |
199 | "bl exc_dispatch\n" \ |
198 | "bl exc_dispatch\n" \ |
200 | :: [exc] "i" (exception) \ |
199 | :: [exc] "i" (exception) \ |
201 | );\ |
200 | );\ |
202 | 201 | ||
203 | /** General exception handler. |
202 | /** General exception handler. |
204 | * |
203 | * |
205 | * Stores registers, dispatches the exception, |
204 | * Stores registers, dispatches the exception, |
206 | * and finally restores registers and returns from exception processing. |
205 | * and finally restores registers and returns from exception processing. |
207 | * |
206 | * |
208 | * @param exception Exception number. |
207 | * @param exception Exception number. |
209 | */ |
208 | */ |
210 | #define PROCESS_EXCEPTION(exception) \ |
209 | #define PROCESS_EXCEPTION(exception) \ |
211 | setup_stack_and_save_regs(); \ |
210 | setup_stack_and_save_regs(); \ |
212 | CALL_EXC_DISPATCH(exception) \ |
211 | CALL_EXC_DISPATCH(exception) \ |
213 | load_regs(); |
212 | load_regs(); |
214 | 213 | ||
215 | /** Updates specified exception vector to jump to given handler. |
214 | /** Updates specified exception vector to jump to given handler. |
216 | * |
215 | * |
217 | * Addresses of handlers are stored in memory following exception vectors. |
216 | * Addresses of handlers are stored in memory following exception vectors. |
218 | */ |
217 | */ |
219 | static void install_handler(unsigned handler_addr, unsigned *vector) |
218 | static void install_handler(unsigned handler_addr, unsigned *vector) |
220 | { |
219 | { |
221 | /* relative address (related to exc. vector) of the word |
220 | /* relative address (related to exc. vector) of the word |
222 | * where handler's address is stored |
221 | * where handler's address is stored |
223 | */ |
222 | */ |
224 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - |
223 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - |
225 | PREFETCH_OFFSET; |
224 | PREFETCH_OFFSET; |
226 | 225 | ||
227 | /* make it LDR instruction and store at exception vector */ |
226 | /* make it LDR instruction and store at exception vector */ |
228 | *vector = handler_address_ptr | LDR_OPCODE; |
227 | *vector = handler_address_ptr | LDR_OPCODE; |
229 | smc_coherence(*vector); |
228 | smc_coherence(*vector); |
230 | 229 | ||
231 | /* store handler's address */ |
230 | /* store handler's address */ |
232 | *(vector + EXC_VECTORS) = handler_addr; |
231 | *(vector + EXC_VECTORS) = handler_addr; |
233 | 232 | ||
234 | } |
233 | } |
235 | 234 | ||
236 | /** Low-level Reset Exception handler. */ |
235 | /** Low-level Reset Exception handler. */ |
237 | static void reset_exception_entry(void) |
236 | static void reset_exception_entry(void) |
238 | { |
237 | { |
239 | PROCESS_EXCEPTION(EXC_RESET); |
238 | PROCESS_EXCEPTION(EXC_RESET); |
240 | } |
239 | } |
241 | 240 | ||
242 | /** Low-level Software Interrupt Exception handler. */ |
241 | /** Low-level Software Interrupt Exception handler. */ |
243 | static void swi_exception_entry(void) |
242 | static void swi_exception_entry(void) |
244 | { |
243 | { |
245 | PROCESS_EXCEPTION(EXC_SWI); |
244 | PROCESS_EXCEPTION(EXC_SWI); |
246 | } |
245 | } |
247 | 246 | ||
248 | /** Low-level Undefined Instruction Exception handler. */ |
247 | /** Low-level Undefined Instruction Exception handler. */ |
249 | static void undef_instr_exception_entry(void) |
248 | static void undef_instr_exception_entry(void) |
250 | { |
249 | { |
251 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
250 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
252 | } |
251 | } |
253 | 252 | ||
254 | /** Low-level Fast Interrupt Exception handler. */ |
253 | /** Low-level Fast Interrupt Exception handler. */ |
255 | static void fiq_exception_entry(void) |
254 | static void fiq_exception_entry(void) |
256 | { |
255 | { |
257 | PROCESS_EXCEPTION(EXC_FIQ); |
256 | PROCESS_EXCEPTION(EXC_FIQ); |
258 | } |
257 | } |
259 | 258 | ||
260 | /** Low-level Prefetch Abort Exception handler. */ |
259 | /** Low-level Prefetch Abort Exception handler. */ |
261 | static void prefetch_abort_exception_entry(void) |
260 | static void prefetch_abort_exception_entry(void) |
262 | { |
261 | { |
- | 262 | asm volatile ( |
|
263 | asm("sub lr, lr, #4"); |
263 | "sub lr, lr, #4" |
- | 264 | ); |
|
- | 265 | ||
264 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
266 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
265 | } |
267 | } |
266 | 268 | ||
267 | /** Low-level Data Abort Exception handler. */ |
269 | /** Low-level Data Abort Exception handler. */ |
268 | static void data_abort_exception_entry(void) |
270 | static void data_abort_exception_entry(void) |
269 | { |
271 | { |
- | 272 | asm volatile ( |
|
270 | asm("sub lr, lr, #8"); |
273 | "sub lr, lr, #8" |
- | 274 | ); |
|
- | 275 | ||
271 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
276 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
272 | } |
277 | } |
273 | 278 | ||
274 | /** Low-level Interrupt Exception handler. |
279 | /** Low-level Interrupt Exception handler. |
275 | * |
280 | * |
276 | * CPU is switched to Undefined mode before further interrupt processing |
281 | * CPU is switched to Undefined mode before further interrupt processing |
277 | * because of possible occurence of nested interrupt exception, which |
282 | * because of possible occurence of nested interrupt exception, which |
278 | * would overwrite (and thus spoil) stack pointer. |
283 | * would overwrite (and thus spoil) stack pointer. |
279 | */ |
284 | */ |
280 | static void irq_exception_entry(void) |
285 | static void irq_exception_entry(void) |
281 | { |
286 | { |
- | 287 | asm volatile ( |
|
282 | asm("sub lr, lr, #4"); |
288 | "sub lr, lr, #4" |
- | 289 | ); |
|
- | 290 | ||
283 | setup_stack_and_save_regs(); |
291 | setup_stack_and_save_regs(); |
284 | 292 | ||
285 | switch_to_irq_servicing_mode(); |
293 | switch_to_irq_servicing_mode(); |
286 | 294 | ||
287 | CALL_EXC_DISPATCH(EXC_IRQ) |
295 | CALL_EXC_DISPATCH(EXC_IRQ) |
288 | 296 | ||
289 | load_regs(); |
297 | load_regs(); |
290 | } |
298 | } |
291 | 299 | ||
292 | /** Software Interrupt handler. |
300 | /** Software Interrupt handler. |
293 | * |
301 | * |
294 | * Dispatches the syscall. |
302 | * Dispatches the syscall. |
295 | */ |
303 | */ |
296 | static void swi_exception(int exc_no, istate_t *istate) |
304 | static void swi_exception(int exc_no, istate_t *istate) |
297 | { |
305 | { |
298 | istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2, |
306 | istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2, |
299 | istate->r3, istate->r4, istate->r5, istate->r6); |
307 | istate->r3, istate->r4, istate->r5, istate->r6); |
300 | } |
308 | } |
301 | 309 | ||
- | 310 | /** Returns the mask of active interrupts. */ |
|
- | 311 | static inline uint32_t gxemul_irqc_get_sources(void) |
|
- | 312 | { |
|
- | 313 | return *((uint32_t *) gxemul_irqc); |
|
- | 314 | } |
|
- | 315 | ||
302 | /** Interrupt Exception handler. |
316 | /** Interrupt Exception handler. |
303 | * |
317 | * |
304 | * Determines the sources of interrupt and calls their handlers. |
318 | * Determines the sources of interrupt and calls their handlers. |
305 | */ |
319 | */ |
306 | static void irq_exception(int exc_no, istate_t *istate) |
320 | static void irq_exception(int exc_no, istate_t *istate) |
307 | { |
321 | { |
- | 322 | uint32_t sources = gxemul_irqc_get_sources(); |
|
- | 323 | unsigned int i; |
|
- | 324 | ||
- | 325 | for (i = 0; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
|
- | 326 | if (sources & (1 << i)) { |
|
308 | machine_irq_exception(exc_no, istate); |
327 | irq_t *irq = irq_dispatch_and_lock(i); |
- | 328 | if (irq) { |
|
- | 329 | /* The IRQ handler was found. */ |
|
- | 330 | irq->handler(irq); |
|
- | 331 | spinlock_unlock(&irq->lock); |
|
- | 332 | } else { |
|
- | 333 | /* Spurious interrupt.*/ |
|
- | 334 | printf("cpu%d: spurious interrupt (inum=%d)\n", |
|
- | 335 | CPU->id, i); |
|
- | 336 | } |
|
- | 337 | } |
|
- | 338 | } |
|
309 | } |
339 | } |
310 | 340 | ||
311 | /** Fills exception vectors with appropriate exception handlers. */ |
341 | /** Fills exception vectors with appropriate exception handlers. */ |
312 | void install_exception_handlers(void) |
342 | void install_exception_handlers(void) |
313 | { |
343 | { |
314 | install_handler((unsigned) reset_exception_entry, |
344 | install_handler((unsigned) reset_exception_entry, |
315 | (unsigned *) EXC_RESET_VEC); |
345 | (unsigned *) EXC_RESET_VEC); |
316 | 346 | ||
317 | install_handler((unsigned) undef_instr_exception_entry, |
347 | install_handler((unsigned) undef_instr_exception_entry, |
318 | (unsigned *) EXC_UNDEF_INSTR_VEC); |
348 | (unsigned *) EXC_UNDEF_INSTR_VEC); |
319 | 349 | ||
320 | install_handler((unsigned) swi_exception_entry, |
350 | install_handler((unsigned) swi_exception_entry, |
321 | (unsigned *) EXC_SWI_VEC); |
351 | (unsigned *) EXC_SWI_VEC); |
322 | 352 | ||
323 | install_handler((unsigned) prefetch_abort_exception_entry, |
353 | install_handler((unsigned) prefetch_abort_exception_entry, |
324 | (unsigned *) EXC_PREFETCH_ABORT_VEC); |
354 | (unsigned *) EXC_PREFETCH_ABORT_VEC); |
325 | 355 | ||
326 | install_handler((unsigned) data_abort_exception_entry, |
356 | install_handler((unsigned) data_abort_exception_entry, |
327 | (unsigned *) EXC_DATA_ABORT_VEC); |
357 | (unsigned *) EXC_DATA_ABORT_VEC); |
328 | 358 | ||
329 | install_handler((unsigned) irq_exception_entry, |
359 | install_handler((unsigned) irq_exception_entry, |
330 | (unsigned *) EXC_IRQ_VEC); |
360 | (unsigned *) EXC_IRQ_VEC); |
331 | 361 | ||
332 | install_handler((unsigned)fiq_exception_entry, |
362 | install_handler((unsigned) fiq_exception_entry, |
333 | (unsigned *) EXC_FIQ_VEC); |
363 | (unsigned *) EXC_FIQ_VEC); |
334 | } |
364 | } |
335 | 365 | ||
336 | #ifdef HIGH_EXCEPTION_VECTORS |
366 | #ifdef HIGH_EXCEPTION_VECTORS |
337 | /** Activates use of high exception vectors addresses. */ |
367 | /** Activates use of high exception vectors addresses. */ |
338 | static void high_vectors(void) |
368 | static void high_vectors(void) |
339 | { |
369 | { |
340 | uint32_t control_reg; |
370 | uint32_t control_reg; |
341 | 371 | ||
342 | asm volatile ( |
372 | asm volatile ( |
343 | "mrc p15, 0, %[control_reg], c1, c1" |
373 | "mrc p15, 0, %[control_reg], c1, c1" |
344 | : [control_reg] "=r" (control_reg) |
374 | : [control_reg] "=r" (control_reg) |
345 | ); |
375 | ); |
346 | 376 | ||
347 | /* switch on the high vectors bit */ |
377 | /* switch on the high vectors bit */ |
348 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
378 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
349 | 379 | ||
350 | asm volatile ( |
380 | asm volatile ( |
351 | "mcr p15, 0, %[control_reg], c1, c1" |
381 | "mcr p15, 0, %[control_reg], c1, c1" |
352 | :: [control_reg] "r" (control_reg) |
382 | :: [control_reg] "r" (control_reg) |
353 | ); |
383 | ); |
354 | } |
384 | } |
355 | #endif |
385 | #endif |
356 | 386 | ||
357 | /** Initializes exception handling. |
387 | /** Initializes exception handling. |
358 | * |
388 | * |
359 | * Installs low-level exception handlers and then registers |
389 | * Installs low-level exception handlers and then registers |
360 | * exceptions and their handlers to kernel exception dispatcher. |
390 | * exceptions and their handlers to kernel exception dispatcher. |
361 | */ |
391 | */ |
362 | void exception_init(void) |
392 | void exception_init(void) |
363 | { |
393 | { |
364 | #ifdef HIGH_EXCEPTION_VECTORS |
394 | #ifdef HIGH_EXCEPTION_VECTORS |
365 | high_vectors(); |
395 | high_vectors(); |
366 | #endif |
396 | #endif |
367 | install_exception_handlers(); |
397 | install_exception_handlers(); |
368 | 398 | ||
369 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
399 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
370 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", |
400 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", |
371 | (iroutine) prefetch_abort); |
401 | (iroutine) prefetch_abort); |
372 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
402 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
373 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
403 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
374 | } |
404 | } |
375 | 405 | ||
376 | /** Prints #istate_t structure content. |
406 | /** Prints #istate_t structure content. |
377 | * |
407 | * |
378 | * @param istate Structure to be printed. |
408 | * @param istate Structure to be printed. |
379 | */ |
409 | */ |
380 | void print_istate(istate_t *istate) |
410 | void print_istate(istate_t *istate) |
381 | { |
411 | { |
382 | dprintf("istate dump:\n"); |
412 | printf("istate dump:\n"); |
383 | 413 | ||
384 | dprintf(" r0: %x r1: %x r2: %x r3: %x\n", |
414 | printf(" r0: %x r1: %x r2: %x r3: %x\n", |
385 | istate->r0, istate->r1, istate->r2, istate->r3); |
415 | istate->r0, istate->r1, istate->r2, istate->r3); |
386 | dprintf(" r4: %x r5: %x r6: %x r7: %x\n", |
416 | printf(" r4: %x r5: %x r6: %x r7: %x\n", |
387 | istate->r4, istate->r5, istate->r6, istate->r7); |
417 | istate->r4, istate->r5, istate->r6, istate->r7); |
388 | dprintf(" r8: %x r8: %x r10: %x r11: %x\n", |
418 | printf(" r8: %x r8: %x r10: %x r11: %x\n", |
389 | istate->r8, istate->r9, istate->r10, istate->r11); |
419 | istate->r8, istate->r9, istate->r10, istate->r11); |
390 | dprintf(" r12: %x sp: %x lr: %x spsr: %x\n", |
420 | printf(" r12: %x sp: %x lr: %x spsr: %x\n", |
391 | istate->r12, istate->sp, istate->lr, istate->spsr); |
421 | istate->r12, istate->sp, istate->lr, istate->spsr); |
392 | 422 | ||
393 | dprintf(" pc: %x\n", istate->pc); |
423 | printf(" pc: %x\n", istate->pc); |
394 | } |
424 | } |
395 | 425 | ||
396 | /** @} |
426 | /** @} |
397 | */ |
427 | */ |
398 | 428 |