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1 | # |
1 | # |
2 | # Copyright (C) 2005 Ondrej Palkovsky |
2 | # Copyright (C) 2005 Ondrej Palkovsky |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | 29 | ||
30 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
30 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
31 | # and 1 means interrupt with error word |
31 | # and 1 means interrupt with error word |
32 | 32 | ||
33 | 33 | ||
34 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
34 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
35 | 35 | ||
36 | #define __ASM__ |
36 | #define __ASM__ |
37 | #include <arch/pm.h> |
37 | #include <arch/pm.h> |
38 | 38 | ||
39 | .text |
39 | .text |
40 | .global interrupt_handlers |
40 | .global interrupt_handlers |
41 | .global panic_printf |
41 | .global panic_printf |
42 | 42 | ||
43 | panic_printf: |
43 | panic_printf: |
44 | movq $halt, (%rsp) |
44 | movq $halt, (%rsp) |
45 | jmp printf |
45 | jmp printf |
46 | 46 | ||
47 | .global memcpy |
47 | .global memcpy |
48 | memcpy: |
48 | memcpy: |
49 | jmp _memcpy |
49 | jmp _memcpy |
50 | 50 | ||
51 | .global cpuid |
51 | .global cpuid |
52 | .global has_cpuid |
52 | .global has_cpuid |
53 | .global rdtsc |
53 | .global rdtsc |
54 | .global read_efer_flag |
54 | .global read_efer_flag |
55 | .global set_efer_flag |
55 | .global set_efer_flag |
56 | 56 | ||
57 | 57 | ||
- | 58 | # THIS IS USERSPACE CODE |
|
- | 59 | .global utext |
|
- | 60 | utext: |
|
- | 61 | xor %ax,%ax; |
|
- | 62 | mov %ax,%ds; |
|
- | 63 | mov %ax,%es; |
|
- | 64 | mov %ax,%fs; |
|
- | 65 | mov %ax,%gs; |
|
- | 66 | 0: |
|
- | 67 | int $48 |
|
- | 68 | jmp 0b |
|
- | 69 | # not reached |
|
- | 70 | utext_end: |
|
- | 71 | ||
- | 72 | .data |
|
- | 73 | .global utext_size |
|
- | 74 | utext_size: |
|
- | 75 | .long utext_end - utext |
|
- | 76 | ||
- | 77 | ||
58 | ## Determine CPUID support |
78 | ## Determine CPUID support |
59 | # |
79 | # |
60 | # Return 0 in EAX if CPUID is not support, 1 if supported. |
80 | # Return 0 in EAX if CPUID is not support, 1 if supported. |
61 | # |
81 | # |
62 | has_cpuid: |
82 | has_cpuid: |
63 | pushq %rbx |
83 | pushq %rbx |
64 | 84 | ||
65 | pushfq # store flags |
85 | pushfq # store flags |
66 | popq %rax # read flags |
86 | popq %rax # read flags |
67 | movq %rax,%rbx # copy flags |
87 | movq %rax,%rbx # copy flags |
68 | btcl $21,%ebx # swap the ID bit |
88 | btcl $21,%ebx # swap the ID bit |
69 | pushq %rbx |
89 | pushq %rbx |
70 | popfq # propagate the change into flags |
90 | popfq # propagate the change into flags |
71 | pushfq |
91 | pushfq |
72 | popq %rbx # read flags |
92 | popq %rbx # read flags |
73 | andl $(1<<21),%eax # interested only in ID bit |
93 | andl $(1<<21),%eax # interested only in ID bit |
74 | andl $(1<<21),%ebx |
94 | andl $(1<<21),%ebx |
75 | xorl %ebx,%eax # 0 if not supported, 1 if supported |
95 | xorl %ebx,%eax # 0 if not supported, 1 if supported |
76 | 96 | ||
77 | popq %rbx |
97 | popq %rbx |
78 | ret |
98 | ret |
79 | 99 | ||
80 | cpuid: |
100 | cpuid: |
81 | movq %rbx, %r10 # we have to preserve rbx across function calls |
101 | movq %rbx, %r10 # we have to preserve rbx across function calls |
82 | 102 | ||
83 | movl %edi,%eax # load the command into %eax |
103 | movl %edi,%eax # load the command into %eax |
84 | 104 | ||
85 | cpuid |
105 | cpuid |
86 | movl %eax,0(%rsi) |
106 | movl %eax,0(%rsi) |
87 | movl %ebx,4(%rsi) |
107 | movl %ebx,4(%rsi) |
88 | movl %ecx,8(%rsi) |
108 | movl %ecx,8(%rsi) |
89 | movl %edx,12(%rsi) |
109 | movl %edx,12(%rsi) |
90 | 110 | ||
91 | movq %r10, %rbx |
111 | movq %r10, %rbx |
92 | ret |
112 | ret |
93 | 113 | ||
94 | rdtsc: |
114 | rdtsc: |
95 | xorq %rax,%rax |
115 | xorq %rax,%rax |
96 | rdtsc |
116 | rdtsc |
97 | ret |
117 | ret |
98 | 118 | ||
99 | set_efer_flag: |
119 | set_efer_flag: |
100 | movq $0xc0000080, %rcx |
120 | movq $0xc0000080, %rcx |
101 | rdmsr |
121 | rdmsr |
102 | btsl %edi, %eax |
122 | btsl %edi, %eax |
103 | wrmsr |
123 | wrmsr |
104 | ret |
124 | ret |
105 | 125 | ||
106 | read_efer_flag: |
126 | read_efer_flag: |
107 | movq $0xc0000080, %rcx |
127 | movq $0xc0000080, %rcx |
108 | rdmsr |
128 | rdmsr |
109 | ret |
129 | ret |
110 | 130 | ||
111 | # Push all general purpose registers on stack except %rbp, %rsp |
131 | # Push all general purpose registers on stack except %rbp, %rsp |
112 | .macro push_all_gpr |
132 | .macro push_all_gpr |
113 | pushq %rax |
133 | pushq %rax |
114 | pushq %rbx |
134 | pushq %rbx |
115 | pushq %rcx |
135 | pushq %rcx |
116 | pushq %rdx |
136 | pushq %rdx |
117 | pushq %rsi |
137 | pushq %rsi |
118 | pushq %rdi |
138 | pushq %rdi |
119 | pushq %r8 |
139 | pushq %r8 |
120 | pushq %r9 |
140 | pushq %r9 |
121 | pushq %r10 |
141 | pushq %r10 |
122 | pushq %r11 |
142 | pushq %r11 |
123 | pushq %r12 |
143 | pushq %r12 |
124 | pushq %r13 |
144 | pushq %r13 |
125 | pushq %r14 |
145 | pushq %r14 |
126 | pushq %r15 |
146 | pushq %r15 |
127 | .endm |
147 | .endm |
128 | 148 | ||
129 | .macro pop_all_gpr |
149 | .macro pop_all_gpr |
130 | popq %r15 |
150 | popq %r15 |
131 | popq %r14 |
151 | popq %r14 |
132 | popq %r13 |
152 | popq %r13 |
133 | popq %r12 |
153 | popq %r12 |
134 | popq %r11 |
154 | popq %r11 |
135 | popq %r10 |
155 | popq %r10 |
136 | popq %r9 |
156 | popq %r9 |
137 | popq %r8 |
157 | popq %r8 |
138 | popq %rdi |
158 | popq %rdi |
139 | popq %rsi |
159 | popq %rsi |
140 | popq %rdx |
160 | popq %rdx |
141 | popq %rcx |
161 | popq %rcx |
142 | popq %rbx |
162 | popq %rbx |
143 | popq %rax |
163 | popq %rax |
144 | .endm |
164 | .endm |
145 | 165 | ||
146 | ## Declare interrupt handlers |
166 | ## Declare interrupt handlers |
147 | # |
167 | # |
148 | # Declare interrupt handlers for n interrupt |
168 | # Declare interrupt handlers for n interrupt |
149 | # vectors starting at vector i. |
169 | # vectors starting at vector i. |
150 | # |
170 | # |
151 | # The handlers setup data segment registers |
171 | # The handlers setup data segment registers |
152 | # and call trap_dispatcher(). |
172 | # and call trap_dispatcher(). |
153 | # |
173 | # |
154 | .macro handler i n |
174 | .macro handler i n |
155 | pushq %rbp |
175 | pushq %rbp |
156 | movq %rsp,%rbp |
176 | movq %rsp,%rbp |
157 | 177 | ||
158 | push_all_gpr |
178 | push_all_gpr |
159 | 179 | ||
160 | # trap_dispatcher(i, stack) |
180 | # trap_dispatcher(i, stack) |
161 | movq $(\i),%rdi # %rdi - first parameter |
181 | movq $(\i),%rdi # %rdi - first parameter |
162 | movq %rbp, %rsi |
182 | movq %rbp, %rsi |
163 | addq $8, %rsi # %rsi - second parameter - original stack |
183 | addq $8, %rsi # %rsi - second parameter - original stack |
164 | call trap_dispatcher |
184 | call trap_dispatcher |
165 | 185 | ||
166 | # Test if this is interrupt with error word or not |
186 | # Test if this is interrupt with error word or not |
167 | mov $\i,%cl; |
187 | mov $\i,%cl; |
168 | movl $1,%eax; |
188 | movl $1,%eax; |
169 | test $0xe0,%cl; |
189 | test $0xe0,%cl; |
170 | jnz 0f; |
190 | jnz 0f; |
171 | and $0x1f,%cl; |
191 | and $0x1f,%cl; |
172 | shl %cl,%eax; |
192 | shl %cl,%eax; |
173 | and $ERROR_WORD_INTERRUPT_LIST,%eax; |
193 | and $ERROR_WORD_INTERRUPT_LIST,%eax; |
174 | jz 0f; |
194 | jz 0f; |
175 | 195 | ||
176 | 196 | ||
177 | # Return with error word |
197 | # Return with error word |
178 | pop_all_gpr |
198 | pop_all_gpr |
179 | 199 | ||
180 | popq %rbp; |
200 | popq %rbp; |
181 | add $8,%esp; # Skip error word |
201 | add $8,%esp; # Skip error word |
182 | iretq |
202 | iretq |
183 | 203 | ||
184 | 0: |
204 | 0: |
185 | # Return with no error word |
205 | # Return with no error word |
186 | pop_all_gpr |
206 | pop_all_gpr |
187 | 207 | ||
188 | popq %rbp |
208 | popq %rbp |
189 | iretq |
209 | iretq |
190 | 210 | ||
191 | .if (\n-\i)-1 |
211 | .if (\n-\i)-1 |
192 | handler "(\i+1)",\n |
212 | handler "(\i+1)",\n |
193 | .endif |
213 | .endif |
194 | .endm |
214 | .endm |
195 | 215 | ||
196 | interrupt_handlers: |
216 | interrupt_handlers: |
197 | h_start: |
217 | h_start: |
198 | handler 0 IDT_ITEMS |
218 | handler 0 IDT_ITEMS |
199 | # handler 64 128 |
219 | # handler 64 128 |
200 | # handler 128 192 |
220 | # handler 128 192 |
201 | # handler 192 256 |
221 | # handler 192 256 |
202 | h_end: |
222 | h_end: |
203 | 223 | ||
204 | 224 | ||
205 | .data |
225 | .data |
206 | .global interrupt_handler_size |
226 | .global interrupt_handler_size |
207 | 227 | ||
208 | interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS |
228 | interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS |
209 | 229 |