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1 | # |
1 | # |
2 | # Copyright (C) 2005 Jakub Jermar |
2 | # Copyright (C) 2005 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | /** |
29 | /** |
30 | * This file contains two trap tables. |
30 | * This file contains two trap tables. |
31 | * First, trap_table, is the one wich contains handlers implemented by |
31 | * First, trap_table, is the one wich contains handlers implemented by |
32 | * kernel. During initialization, these handlers are copied out to |
32 | * kernel. During initialization, these handlers are copied out to |
33 | * the second trap table, trap_table_save, and the first table is |
33 | * the second trap table, trap_table_save, and the first table is |
34 | * overwritten with copy of OFW's own trap table. The copy is then patched |
34 | * overwritten with copy of OFW's own trap table. The copy is then patched |
35 | * from the trap_table_save. |
35 | * from the trap_table_save. |
36 | * |
36 | * |
37 | * This arrangement is beneficial because kernel handlers stay on their |
37 | * This arrangement is beneficial because kernel handlers stay on their |
38 | * link-time addresses which is good for debugging. |
38 | * link-time addresses which is good for debugging. |
39 | */ |
39 | */ |
40 | 40 | ||
41 | .register %g2, #scratch |
41 | .register %g2, #scratch |
42 | .register %g3, #scratch |
42 | .register %g3, #scratch |
43 | .register %g6, #scratch |
43 | .register %g6, #scratch |
44 | .register %g7, #scratch |
44 | .register %g7, #scratch |
45 | 45 | ||
46 | .text |
46 | .text |
47 | 47 | ||
48 | #include <arch/trap/trap_table.h> |
48 | #include <arch/trap/trap_table.h> |
49 | #include <arch/trap/regwin.h> |
49 | #include <arch/trap/regwin.h> |
50 | #include <arch/trap/interrupt.h> |
50 | #include <arch/trap/interrupt.h> |
51 | #include <arch/trap/exception.h> |
51 | #include <arch/trap/exception.h> |
- | 52 | #include <arch/trap/mmu.h> |
|
52 | #include <arch/stack.h> |
53 | #include <arch/stack.h> |
53 | 54 | ||
54 | #define TABLE_SIZE TRAP_TABLE_SIZE |
55 | #define TABLE_SIZE TRAP_TABLE_SIZE |
55 | #define ENTRY_SIZE TRAP_TABLE_ENTRY_SIZE |
56 | #define ENTRY_SIZE TRAP_TABLE_ENTRY_SIZE |
56 | 57 | ||
57 | /* |
58 | /* |
58 | * Kernel trap table. |
59 | * Kernel trap table. |
59 | */ |
60 | */ |
60 | .align TABLE_SIZE |
61 | .align TABLE_SIZE |
61 | .global trap_table |
62 | .global trap_table |
62 | trap_table: |
63 | trap_table: |
63 | 64 | ||
64 | /* TT = 0x08, TL = 0, instruction_access_exception */ |
65 | /* TT = 0x08, TL = 0, instruction_access_exception */ |
65 | .org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE |
66 | .org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE |
66 | .global instruction_access_exception |
67 | .global instruction_access_exception |
67 | instruction_access_exception: |
68 | instruction_access_exception: |
68 | SIMPLE_HANDLER do_instruction_access_exc |
69 | SIMPLE_HANDLER do_instruction_access_exc |
69 | 70 | ||
70 | /* TT = 0x24, TL = 0, clean_window handler */ |
71 | /* TT = 0x24, TL = 0, clean_window handler */ |
71 | .org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE |
72 | .org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE |
72 | .global clean_window_handler |
73 | .global clean_window_handler |
73 | clean_window_handler: |
74 | clean_window_handler: |
74 | CLEAN_WINDOW_HANDLER |
75 | CLEAN_WINDOW_HANDLER |
75 | 76 | ||
76 | /* TT = 0x34, TL = 0, mem_address_not_aligned */ |
77 | /* TT = 0x34, TL = 0, mem_address_not_aligned */ |
77 | .org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE |
78 | .org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE |
78 | .global mem_address_not_aligned |
79 | .global mem_address_not_aligned |
79 | mem_address_not_aligned: |
80 | mem_address_not_aligned: |
80 | SIMPLE_HANDLER do_mem_address_not_aligned |
81 | SIMPLE_HANDLER do_mem_address_not_aligned |
81 | 82 | ||
82 | /* TT = 0x41, TL = 0, interrupt_level_1 handler */ |
83 | /* TT = 0x41, TL = 0, interrupt_level_1 handler */ |
83 | .org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE |
84 | .org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE |
84 | .global interrupt_level_1_handler |
85 | .global interrupt_level_1_handler |
85 | interrupt_level_1_handler: |
86 | interrupt_level_1_handler: |
86 | INTERRUPT_LEVEL_N_HANDLER 1 |
87 | INTERRUPT_LEVEL_N_HANDLER 1 |
87 | 88 | ||
88 | /* TT = 0x42, TL = 0, interrupt_level_2 handler */ |
89 | /* TT = 0x42, TL = 0, interrupt_level_2 handler */ |
89 | .org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE |
90 | .org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE |
90 | .global interrupt_level_2_handler |
91 | .global interrupt_level_2_handler |
91 | interrupt_level_2_handler: |
92 | interrupt_level_2_handler: |
92 | INTERRUPT_LEVEL_N_HANDLER 2 |
93 | INTERRUPT_LEVEL_N_HANDLER 2 |
93 | 94 | ||
94 | /* TT = 0x43, TL = 0, interrupt_level_3 handler */ |
95 | /* TT = 0x43, TL = 0, interrupt_level_3 handler */ |
95 | .org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE |
96 | .org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE |
96 | .global interrupt_level_3_handler |
97 | .global interrupt_level_3_handler |
97 | interrupt_level_3_handler: |
98 | interrupt_level_3_handler: |
98 | INTERRUPT_LEVEL_N_HANDLER 3 |
99 | INTERRUPT_LEVEL_N_HANDLER 3 |
99 | 100 | ||
100 | /* TT = 0x44, TL = 0, interrupt_level_4 handler */ |
101 | /* TT = 0x44, TL = 0, interrupt_level_4 handler */ |
101 | .org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE |
102 | .org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE |
102 | .global interrupt_level_4_handler |
103 | .global interrupt_level_4_handler |
103 | interrupt_level_4_handler: |
104 | interrupt_level_4_handler: |
104 | INTERRUPT_LEVEL_N_HANDLER 4 |
105 | INTERRUPT_LEVEL_N_HANDLER 4 |
105 | 106 | ||
106 | /* TT = 0x45, TL = 0, interrupt_level_5 handler */ |
107 | /* TT = 0x45, TL = 0, interrupt_level_5 handler */ |
107 | .org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE |
108 | .org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE |
108 | .global interrupt_level_5_handler |
109 | .global interrupt_level_5_handler |
109 | interrupt_level_5_handler: |
110 | interrupt_level_5_handler: |
110 | INTERRUPT_LEVEL_N_HANDLER 5 |
111 | INTERRUPT_LEVEL_N_HANDLER 5 |
111 | 112 | ||
112 | /* TT = 0x46, TL = 0, interrupt_level_6 handler */ |
113 | /* TT = 0x46, TL = 0, interrupt_level_6 handler */ |
113 | .org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE |
114 | .org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE |
114 | .global interrupt_level_6_handler |
115 | .global interrupt_level_6_handler |
115 | interrupt_level_6_handler: |
116 | interrupt_level_6_handler: |
116 | INTERRUPT_LEVEL_N_HANDLER 6 |
117 | INTERRUPT_LEVEL_N_HANDLER 6 |
117 | 118 | ||
118 | /* TT = 0x47, TL = 0, interrupt_level_7 handler */ |
119 | /* TT = 0x47, TL = 0, interrupt_level_7 handler */ |
119 | .org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE |
120 | .org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE |
120 | .global interrupt_level_7_handler |
121 | .global interrupt_level_7_handler |
121 | interrupt_level_7_handler: |
122 | interrupt_level_7_handler: |
122 | INTERRUPT_LEVEL_N_HANDLER 7 |
123 | INTERRUPT_LEVEL_N_HANDLER 7 |
123 | 124 | ||
124 | /* TT = 0x48, TL = 0, interrupt_level_8 handler */ |
125 | /* TT = 0x48, TL = 0, interrupt_level_8 handler */ |
125 | .org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE |
126 | .org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE |
126 | .global interrupt_level_8_handler |
127 | .global interrupt_level_8_handler |
127 | interrupt_level_8_handler: |
128 | interrupt_level_8_handler: |
128 | INTERRUPT_LEVEL_N_HANDLER 8 |
129 | INTERRUPT_LEVEL_N_HANDLER 8 |
129 | 130 | ||
130 | /* TT = 0x49, TL = 0, interrupt_level_9 handler */ |
131 | /* TT = 0x49, TL = 0, interrupt_level_9 handler */ |
131 | .org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE |
132 | .org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE |
132 | .global interrupt_level_9_handler |
133 | .global interrupt_level_9_handler |
133 | interrupt_level_9_handler: |
134 | interrupt_level_9_handler: |
134 | INTERRUPT_LEVEL_N_HANDLER 9 |
135 | INTERRUPT_LEVEL_N_HANDLER 9 |
135 | 136 | ||
136 | /* TT = 0x4a, TL = 0, interrupt_level_10 handler */ |
137 | /* TT = 0x4a, TL = 0, interrupt_level_10 handler */ |
137 | .org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE |
138 | .org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE |
138 | .global interrupt_level_10_handler |
139 | .global interrupt_level_10_handler |
139 | interrupt_level_10_handler: |
140 | interrupt_level_10_handler: |
140 | INTERRUPT_LEVEL_N_HANDLER 10 |
141 | INTERRUPT_LEVEL_N_HANDLER 10 |
141 | 142 | ||
142 | /* TT = 0x4b, TL = 0, interrupt_level_11 handler */ |
143 | /* TT = 0x4b, TL = 0, interrupt_level_11 handler */ |
143 | .org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE |
144 | .org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE |
144 | .global interrupt_level_11_handler |
145 | .global interrupt_level_11_handler |
145 | interrupt_level_11_handler: |
146 | interrupt_level_11_handler: |
146 | INTERRUPT_LEVEL_N_HANDLER 11 |
147 | INTERRUPT_LEVEL_N_HANDLER 11 |
147 | 148 | ||
148 | /* TT = 0x4c, TL = 0, interrupt_level_12 handler */ |
149 | /* TT = 0x4c, TL = 0, interrupt_level_12 handler */ |
149 | .org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE |
150 | .org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE |
150 | .global interrupt_level_12_handler |
151 | .global interrupt_level_12_handler |
151 | interrupt_level_12_handler: |
152 | interrupt_level_12_handler: |
152 | INTERRUPT_LEVEL_N_HANDLER 12 |
153 | INTERRUPT_LEVEL_N_HANDLER 12 |
153 | 154 | ||
154 | /* TT = 0x4d, TL = 0, interrupt_level_13 handler */ |
155 | /* TT = 0x4d, TL = 0, interrupt_level_13 handler */ |
155 | .org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE |
156 | .org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE |
156 | .global interrupt_level_13_handler |
157 | .global interrupt_level_13_handler |
157 | interrupt_level_13_handler: |
158 | interrupt_level_13_handler: |
158 | INTERRUPT_LEVEL_N_HANDLER 13 |
159 | INTERRUPT_LEVEL_N_HANDLER 13 |
159 | 160 | ||
160 | /* TT = 0x4e, TL = 0, interrupt_level_14 handler */ |
161 | /* TT = 0x4e, TL = 0, interrupt_level_14 handler */ |
161 | .org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE |
162 | .org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE |
162 | .global interrupt_level_14_handler |
163 | .global interrupt_level_14_handler |
163 | interrupt_level_14_handler: |
164 | interrupt_level_14_handler: |
164 | INTERRUPT_LEVEL_N_HANDLER 14 |
165 | INTERRUPT_LEVEL_N_HANDLER 14 |
165 | 166 | ||
166 | /* TT = 0x4f, TL = 0, interrupt_level_15 handler */ |
167 | /* TT = 0x4f, TL = 0, interrupt_level_15 handler */ |
167 | .org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE |
168 | .org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE |
168 | .global interrupt_level_15_handler |
169 | .global interrupt_level_15_handler |
169 | interrupt_level_15_handler: |
170 | interrupt_level_15_handler: |
170 | INTERRUPT_LEVEL_N_HANDLER 15 |
171 | INTERRUPT_LEVEL_N_HANDLER 15 |
171 | 172 | ||
172 | /* TT = 0x60, TL = 0, interrupt_vector_trap handler */ |
173 | /* TT = 0x60, TL = 0, interrupt_vector_trap handler */ |
173 | .org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE |
174 | .org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE |
174 | .global interrupt_vector_trap_handler |
175 | .global interrupt_vector_trap_handler |
175 | interrupt_vector_trap_handler: |
176 | interrupt_vector_trap_handler: |
176 | INTERRUPT_VECTOR_TRAP_HANDLER |
177 | INTERRUPT_VECTOR_TRAP_HANDLER |
177 | 178 | ||
- | 179 | /* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */ |
|
- | 180 | .org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE |
|
- | 181 | .global fast_instruction_access_mmu_miss_handler |
|
- | 182 | fast_instruction_access_mmu_miss_handler: |
|
- | 183 | FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER |
|
- | 184 | ||
- | 185 | /* TT = 0x68, TL = 0, fast_data_access_MMU_miss */ |
|
- | 186 | .org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE |
|
- | 187 | .global fast_data_access_mmu_miss_handler |
|
- | 188 | fast_data_access_mmu_miss_handler: |
|
- | 189 | FAST_DATA_ACCESS_MMU_MISS_HANDLER |
|
- | 190 | ||
- | 191 | /* TT = 0x6c, TL = 0, fast_data_access_protection */ |
|
- | 192 | .org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE |
|
- | 193 | .global fast_data_access_protection_handler |
|
- | 194 | fast_data_access_protection_handler: |
|
- | 195 | FAST_DATA_ACCESS_PROTECTION_HANDLER |
|
- | 196 | ||
178 | /* TT = 0x80, TL = 0, spill_0_normal handler */ |
197 | /* TT = 0x80, TL = 0, spill_0_normal handler */ |
179 | .org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE |
198 | .org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE |
180 | .global spill_0_normal |
199 | .global spill_0_normal |
181 | spill_0_normal: |
200 | spill_0_normal: |
182 | SPILL_NORMAL_HANDLER |
201 | SPILL_NORMAL_HANDLER |
183 | 202 | ||
184 | /* TT = 0xc0, TL = 0, fill_0_normal handler */ |
203 | /* TT = 0xc0, TL = 0, fill_0_normal handler */ |
185 | .org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE |
204 | .org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE |
186 | .global fill_0_normal |
205 | .global fill_0_normal |
187 | fill_0_normal: |
206 | fill_0_normal: |
188 | FILL_NORMAL_HANDLER |
207 | FILL_NORMAL_HANDLER |
189 | 208 | ||
190 | /* |
209 | /* |
191 | * Handlers for TL>0. |
210 | * Handlers for TL>0. |
192 | */ |
211 | */ |
193 | 212 | ||
194 | /* TT = 0x08, TL > 0, instruction_access_exception */ |
213 | /* TT = 0x08, TL > 0, instruction_access_exception */ |
195 | .org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE |
214 | .org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE |
196 | .global instruction_access_exception_high |
215 | .global instruction_access_exception_high |
197 | instruction_access_exception_high: |
216 | instruction_access_exception_high: |
198 | SIMPLE_HANDLER do_instruction_access_exc |
217 | SIMPLE_HANDLER do_instruction_access_exc |
199 | 218 | ||
200 | /* TT = 0x24, TL > 0, clean_window handler */ |
219 | /* TT = 0x24, TL > 0, clean_window handler */ |
201 | .org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE |
220 | .org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE |
202 | .global clean_window_handler_high |
221 | .global clean_window_handler_high |
203 | clean_window_handler_high: |
222 | clean_window_handler_high: |
204 | CLEAN_WINDOW_HANDLER |
223 | CLEAN_WINDOW_HANDLER |
205 | 224 | ||
206 | /* TT = 0x34, TL > 0, mem_address_not_aligned */ |
225 | /* TT = 0x34, TL > 0, mem_address_not_aligned */ |
207 | .org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE |
226 | .org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE |
208 | .global mem_address_not_aligned_high |
227 | .global mem_address_not_aligned_high |
209 | mem_address_not_aligned_high: |
228 | mem_address_not_aligned_high: |
210 | SIMPLE_HANDLER do_mem_address_not_aligned |
229 | SIMPLE_HANDLER do_mem_address_not_aligned |
211 | 230 | ||
- | 231 | /* TT = 0x64, TL > 0, fast_instruction_access_MMU_miss */ |
|
- | 232 | .org trap_table + (TT_FAST_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE |
|
- | 233 | .global fast_instruction_access_mmu_miss_handler_high |
|
- | 234 | fast_instruction_access_mmu_miss_handler_high: |
|
- | 235 | FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER |
|
- | 236 | ||
- | 237 | /* TT = 0x68, TL > 0, fast_data_access_MMU_miss */ |
|
- | 238 | .org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE |
|
- | 239 | .global fast_data_access_mmu_miss_handler_high |
|
- | 240 | fast_data_access_mmu_miss_handler_high: |
|
- | 241 | FAST_DATA_ACCESS_MMU_MISS_HANDLER |
|
- | 242 | ||
- | 243 | /* TT = 0x6c, TL > 0, fast_data_access_protection */ |
|
- | 244 | .org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE |
|
- | 245 | .global fast_data_access_protection_handler_high |
|
- | 246 | fast_data_access_protection_handler_high: |
|
- | 247 | FAST_DATA_ACCESS_PROTECTION_HANDLER |
|
- | 248 | ||
212 | /* TT = 0x80, TL > 0, spill_0_normal handler */ |
249 | /* TT = 0x80, TL > 0, spill_0_normal handler */ |
213 | .org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE |
250 | .org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE |
214 | .global spill_0_normal_high |
251 | .global spill_0_normal_high |
215 | spill_0_normal_high: |
252 | spill_0_normal_high: |
216 | SPILL_NORMAL_HANDLER |
253 | SPILL_NORMAL_HANDLER |
217 | 254 | ||
218 | /* TT = 0xc0, TL > 0, fill_0_normal handler */ |
255 | /* TT = 0xc0, TL > 0, fill_0_normal handler */ |
219 | .org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE |
256 | .org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE |
220 | .global fill_0_normal_high |
257 | .global fill_0_normal_high |
221 | fill_0_normal_high: |
258 | fill_0_normal_high: |
222 | FILL_NORMAL_HANDLER |
259 | FILL_NORMAL_HANDLER |
223 | 260 | ||
224 | 261 | ||
225 | 262 | ||
226 | /* |
263 | /* |
227 | * Save trap table. |
264 | * Save trap table. |
228 | */ |
265 | */ |
229 | .align TABLE_SIZE |
266 | .align TABLE_SIZE |
230 | .global trap_table_save |
267 | .global trap_table_save |
231 | trap_table_save: |
268 | trap_table_save: |
232 | .space TABLE_SIZE, 0 |
269 | .space TABLE_SIZE, 0 |
233 | 270 | ||
234 | 271 | ||
235 | /* Preemptible trap handler. |
272 | /* Preemptible trap handler. |
236 | * |
273 | * |
237 | * This trap handler makes arrangements to |
274 | * This trap handler makes arrangements to |
238 | * make calling scheduler() possible. |
275 | * make calling scheduler() possible. |
239 | * |
276 | * |
240 | * The caller is responsible for doing save |
277 | * The caller is responsible for doing save |
241 | * and allocating PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE |
278 | * and allocating PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE |
242 | * bytes on stack. |
279 | * bytes on stack. |
243 | * |
280 | * |
244 | * Input registers: |
281 | * Input registers: |
245 | * %l0 Address of function to call. |
282 | * %l0 Address of function to call. |
246 | * Output registers: |
283 | * Output registers: |
247 | * %l1 - %l7 Copy of %g1 - %g7 |
284 | * %l1 - %l7 Copy of %g1 - %g7 |
248 | */ |
285 | */ |
249 | .global preemptible_handler |
286 | .global preemptible_handler |
250 | preemptible_handler: |
287 | preemptible_handler: |
251 | /* |
288 | /* |
252 | * Save TSTATE, TPC, TNPC and PSTATE aside. |
289 | * Save TSTATE, TPC, TNPC and PSTATE aside. |
253 | */ |
290 | */ |
254 | rdpr %tstate, %g1 |
291 | rdpr %tstate, %g1 |
255 | rdpr %tpc, %g2 |
292 | rdpr %tpc, %g2 |
256 | rdpr %tnpc, %g3 |
293 | rdpr %tnpc, %g3 |
257 | rdpr %pstate, %g4 |
294 | rdpr %pstate, %g4 |
258 | 295 | ||
259 | stx %g1, [%fp + STACK_BIAS + SAVED_TSTATE] |
296 | stx %g1, [%fp + STACK_BIAS + SAVED_TSTATE] |
260 | stx %g2, [%fp + STACK_BIAS + SAVED_TPC] |
297 | stx %g2, [%fp + STACK_BIAS + SAVED_TPC] |
261 | stx %g3, [%fp + STACK_BIAS + SAVED_TNPC] |
298 | stx %g3, [%fp + STACK_BIAS + SAVED_TNPC] |
262 | stx %g4, [%fp + STACK_BIAS + SAVED_PSTATE] |
299 | stx %g4, [%fp + STACK_BIAS + SAVED_PSTATE] |
263 | 300 | ||
264 | /* |
301 | /* |
265 | * Write 0 to TL. |
302 | * Write 0 to TL. |
266 | */ |
303 | */ |
267 | wrpr %g0, 0, %tl |
304 | wrpr %g0, 0, %tl |
268 | 305 | ||
269 | /* |
306 | /* |
270 | * Alter PSTATE. |
307 | * Alter PSTATE. |
271 | * - switch to normal globals. |
308 | * - switch to normal globals. |
272 | */ |
309 | */ |
273 | and %g4, ~1, %g4 ! mask alternate globals |
310 | and %g4, ~1, %g4 ! mask alternate globals |
274 | wrpr %g4, 0, %pstate |
311 | wrpr %g4, 0, %pstate |
275 | 312 | ||
276 | /* |
313 | /* |
277 | * Save the normal globals. |
314 | * Save the normal globals. |
278 | */ |
315 | */ |
279 | SAVE_GLOBALS |
316 | SAVE_GLOBALS |
280 | 317 | ||
281 | /* |
318 | /* |
282 | * Call the higher-level handler. |
319 | * Call the higher-level handler. |
283 | */ |
320 | */ |
284 | call %l0 |
321 | call %l0 |
285 | nop |
322 | nop |
286 | 323 | ||
287 | /* |
324 | /* |
288 | * Restore the normal global register set. |
325 | * Restore the normal global register set. |
289 | */ |
326 | */ |
290 | RESTORE_GLOBALS |
327 | RESTORE_GLOBALS |
291 | 328 | ||
292 | /* |
329 | /* |
293 | * Restore PSTATE from saved copy. |
330 | * Restore PSTATE from saved copy. |
294 | * Alternate globals become active. |
331 | * Alternate globals become active. |
295 | */ |
332 | */ |
296 | ldx [%fp + STACK_BIAS + SAVED_PSTATE], %l4 |
333 | ldx [%fp + STACK_BIAS + SAVED_PSTATE], %l4 |
297 | wrpr %l4, 0, %pstate |
334 | wrpr %l4, 0, %pstate |
298 | 335 | ||
299 | /* |
336 | /* |
300 | * Write 1 to TL. |
337 | * Write 1 to TL. |
301 | */ |
338 | */ |
302 | wrpr %g0, 1, %tl |
339 | wrpr %g0, 1, %tl |
303 | 340 | ||
304 | /* |
341 | /* |
305 | * Read TSTATE, TPC and TNPC from saved copy. |
342 | * Read TSTATE, TPC and TNPC from saved copy. |
306 | */ |
343 | */ |
307 | ldx [%fp + STACK_BIAS + SAVED_TSTATE], %g1 |
344 | ldx [%fp + STACK_BIAS + SAVED_TSTATE], %g1 |
308 | ldx [%fp + STACK_BIAS + SAVED_TPC], %g2 |
345 | ldx [%fp + STACK_BIAS + SAVED_TPC], %g2 |
309 | ldx [%fp + STACK_BIAS + SAVED_TNPC], %g3 |
346 | ldx [%fp + STACK_BIAS + SAVED_TNPC], %g3 |
310 | 347 | ||
311 | /* |
348 | /* |
312 | * Do restore to match the save instruction from the top-level handler. |
349 | * Do restore to match the save instruction from the top-level handler. |
313 | */ |
350 | */ |
314 | restore |
351 | restore |
315 | 352 | ||
316 | /* |
353 | /* |
317 | * On execution of retry instruction, CWP will be restored from TSTATE register. |
354 | * On execution of retry instruction, CWP will be restored from TSTATE register. |
318 | * However, because of scheduling, it is possible that CWP in saved TSTATE |
355 | * However, because of scheduling, it is possible that CWP in saved TSTATE |
319 | * is different from current CWP. The following chunk of code fixes CWP |
356 | * is different from current CWP. The following chunk of code fixes CWP |
320 | * in the saved copy of TSTATE. |
357 | * in the saved copy of TSTATE. |
321 | */ |
358 | */ |
322 | rdpr %cwp, %g4 ! read current CWP |
359 | rdpr %cwp, %g4 ! read current CWP |
323 | and %g1, ~0x1f, %g1 ! clear CWP field in saved TSTATE |
360 | and %g1, ~0x1f, %g1 ! clear CWP field in saved TSTATE |
324 | or %g1, %g4, %g1 ! write current CWP to TSTATE |
361 | or %g1, %g4, %g1 ! write current CWP to TSTATE |
325 | 362 | ||
326 | /* |
363 | /* |
327 | * Restore TSTATE, TPC and TNPC from saved copies. |
364 | * Restore TSTATE, TPC and TNPC from saved copies. |
328 | */ |
365 | */ |
329 | wrpr %g1, 0, %tstate |
366 | wrpr %g1, 0, %tstate |
330 | wrpr %g2, 0, %tpc |
367 | wrpr %g2, 0, %tpc |
331 | wrpr %g3, 0, %tnpc |
368 | wrpr %g3, 0, %tnpc |
332 | 369 | ||
333 | /* |
370 | /* |
334 | * Return from interrupt. |
371 | * Return from interrupt. |
335 | */ |
372 | */ |
336 | retry |
373 | retry |
337 | 374 | ||
338 | 375 | ||
339 |
|
376 |
|
340 | 377 | ||
341 | 378 | ||
342 | 379 |