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1 | /* |
1 | /* |
2 | * Copyright (c) 2003-2004 Jakub Jermar |
2 | * Copyright (c) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup mips32 |
29 | /** @addtogroup mips32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_mips32_CP0_H_ |
35 | #ifndef KERN_mips32_CP0_H_ |
36 | #define KERN_mips32_CP0_H_ |
36 | #define KERN_mips32_CP0_H_ |
37 | 37 | ||
38 | #include <arch/types.h> |
38 | #include <arch/types.h> |
39 | 39 | ||
40 | #define cp0_status_ie_enabled_bit (1 << 0) |
40 | #define cp0_status_ie_enabled_bit (1 << 0) |
41 | #define cp0_status_exl_exception_bit (1 << 1) |
41 | #define cp0_status_exl_exception_bit (1 << 1) |
42 | #define cp0_status_erl_error_bit (1 << 2) |
42 | #define cp0_status_erl_error_bit (1 << 2) |
43 | #define cp0_status_um_bit (1 << 4) |
43 | #define cp0_status_um_bit (1 << 4) |
44 | #define cp0_status_bev_bootstrap_bit (1 << 22) |
44 | #define cp0_status_bev_bootstrap_bit (1 << 22) |
45 | #define cp0_status_fpu_bit (1 << 29) |
45 | #define cp0_status_fpu_bit (1 << 29) |
46 | 46 | ||
47 | #define cp0_status_im_shift 8 |
47 | #define cp0_status_im_shift 8 |
48 | #define cp0_status_im_mask 0xff00 |
48 | #define cp0_status_im_mask 0xff00 |
49 | 49 | ||
50 | #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) |
50 | #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) |
51 | #define cp0_cause_coperr(cause) ((cause >> 28) & 0x3) |
51 | #define cp0_cause_coperr(cause) ((cause >> 28) & 0x3) |
52 | 52 | ||
53 | #define fpu_cop_id 1 |
53 | #define fpu_cop_id 1 |
54 | 54 | ||
55 | /* |
55 | /* |
56 | * Magic value for use in msim. |
56 | * Magic value for use in msim. |
57 | */ |
57 | */ |
58 | #define cp0_compare_value 100000 |
58 | #define cp0_compare_value 100000 |
59 | 59 | ||
60 | #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
60 | #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
61 | #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
61 | #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
62 | #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1 << (cp0_status_im_shift + (it)))) |
62 | #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1 << (cp0_status_im_shift + (it)))) |
63 | #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1 << (cp0_status_im_shift + (it)))) |
63 | #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1 << (cp0_status_im_shift + (it)))) |
64 | 64 | ||
65 | #define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \ |
65 | #define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \ |
66 | { \ |
66 | { \ |
67 | uint32_t retval; \ |
67 | uint32_t retval; \ |
68 | asm("mfc0 %0, $" #reg : "=r"(retval)); \ |
68 | asm("mfc0 %0, $" #reg : "=r"(retval)); \ |
69 | return retval; \ |
69 | return retval; \ |
70 | } |
70 | } |
71 | 71 | ||
72 | #define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \ |
72 | #define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \ |
73 | { \ |
73 | { \ |
74 | asm("mtc0 %0, $" #reg : : "r"(val) ); \ |
74 | asm("mtc0 %0, $" #reg : : "r"(val) ); \ |
75 | } |
75 | } |
76 | 76 | ||
77 | GEN_READ_CP0(index, 0); |
77 | GEN_READ_CP0(index, 0); |
78 | GEN_WRITE_CP0(index, 0); |
78 | GEN_WRITE_CP0(index, 0); |
79 | 79 | ||
80 | GEN_READ_CP0(random, 1); |
80 | GEN_READ_CP0(random, 1); |
81 | 81 | ||
82 | GEN_READ_CP0(entry_lo0, 2); |
82 | GEN_READ_CP0(entry_lo0, 2); |
83 | GEN_WRITE_CP0(entry_lo0, 2); |
83 | GEN_WRITE_CP0(entry_lo0, 2); |
84 | 84 | ||
85 | GEN_READ_CP0(entry_lo1, 3); |
85 | GEN_READ_CP0(entry_lo1, 3); |
86 | GEN_WRITE_CP0(entry_lo1, 3); |
86 | GEN_WRITE_CP0(entry_lo1, 3); |
87 | 87 | ||
88 | GEN_READ_CP0(context, 4); |
88 | GEN_READ_CP0(context, 4); |
89 | GEN_WRITE_CP0(context, 4); |
89 | GEN_WRITE_CP0(context, 4); |
90 | 90 | ||
91 | GEN_READ_CP0(pagemask, 5); |
91 | GEN_READ_CP0(pagemask, 5); |
92 | GEN_WRITE_CP0(pagemask, 5); |
92 | GEN_WRITE_CP0(pagemask, 5); |
93 | 93 | ||
94 | GEN_READ_CP0(wired, 6); |
94 | GEN_READ_CP0(wired, 6); |
95 | GEN_WRITE_CP0(wired, 6); |
95 | GEN_WRITE_CP0(wired, 6); |
96 | 96 | ||
97 | GEN_READ_CP0(badvaddr, 8); |
97 | GEN_READ_CP0(badvaddr, 8); |
98 | 98 | ||
99 | GEN_READ_CP0(count, 9); |
99 | GEN_READ_CP0(count, 9); |
100 | GEN_WRITE_CP0(count, 9); |
100 | GEN_WRITE_CP0(count, 9); |
101 | 101 | ||
102 | GEN_READ_CP0(entry_hi, 10); |
102 | GEN_READ_CP0(entry_hi, 10); |
103 | GEN_WRITE_CP0(entry_hi, 10); |
103 | GEN_WRITE_CP0(entry_hi, 10); |
104 | 104 | ||
105 | GEN_READ_CP0(compare, 11); |
105 | GEN_READ_CP0(compare, 11); |
106 | GEN_WRITE_CP0(compare, 11); |
106 | GEN_WRITE_CP0(compare, 11); |
107 | 107 | ||
108 | GEN_READ_CP0(status, 12); |
108 | GEN_READ_CP0(status, 12); |
109 | GEN_WRITE_CP0(status, 12); |
109 | GEN_WRITE_CP0(status, 12); |
110 | 110 | ||
111 | GEN_READ_CP0(cause, 13); |
111 | GEN_READ_CP0(cause, 13); |
112 | GEN_WRITE_CP0(cause, 13); |
112 | GEN_WRITE_CP0(cause, 13); |
113 | 113 | ||
114 | GEN_READ_CP0(epc, 14); |
114 | GEN_READ_CP0(epc, 14); |
115 | GEN_WRITE_CP0(epc, 14); |
115 | GEN_WRITE_CP0(epc, 14); |
116 | 116 | ||
117 | GEN_READ_CP0(prid, 15); |
117 | GEN_READ_CP0(prid, 15); |
118 | 118 | ||
119 | #endif |
119 | #endif |
120 | 120 | ||
121 | /** @} |
121 | /** @} |
122 | */ |
122 | */ |
123 | 123 |