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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32mm |
29 | /** @addtogroup arm32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * @brief Page fault related functions. |
33 | * @brief Page fault related functions. |
34 | */ |
34 | */ |
35 | #include <panic.h> |
35 | #include <panic.h> |
36 | #include <arch/exception.h> |
36 | #include <arch/exception.h> |
37 | #include <arch/debug/print.h> |
37 | #include <arch/debug/print.h> |
38 | #include <arch/mm/page_fault.h> |
38 | #include <arch/mm/page_fault.h> |
39 | #include <mm/as.h> |
39 | #include <mm/as.h> |
40 | #include <genarch/mm/page_pt.h> |
40 | #include <genarch/mm/page_pt.h> |
41 | #include <arch.h> |
41 | #include <arch.h> |
42 | #include <interrupt.h> |
42 | #include <interrupt.h> |
43 | 43 | ||
44 | - | ||
45 | /** Returns value stored in fault status register. |
44 | /** Returns value stored in fault status register. |
46 | * |
45 | * |
47 | * @return Value stored in CP15 fault status register (FSR). |
46 | * @return Value stored in CP15 fault status register (FSR). |
48 | */ |
47 | */ |
49 | static inline fault_status_t read_fault_status_register(void) |
48 | static inline fault_status_t read_fault_status_register(void) |
50 | { |
49 | { |
51 | fault_status_union_t fsu; |
50 | fault_status_union_t fsu; |
52 | 51 | ||
53 | // fault status is stored in CP15 register 5 |
52 | /* fault status is stored in CP15 register 5 */ |
54 | asm volatile ( |
53 | asm volatile ( |
55 | "mrc p15, 0, %0, c5, c0, 0" |
54 | "mrc p15, 0, %0, c5, c0, 0" |
56 | : "=r"(fsu.dummy) |
55 | : "=r"(fsu.dummy) |
57 | ); |
56 | ); |
58 | return fsu.fs; |
57 | return fsu.fs; |
59 | } |
58 | } |
60 | 59 | ||
61 | - | ||
62 | /** Returns FAR (fault address register) content. |
60 | /** Returns FAR (fault address register) content. |
63 | * |
61 | * |
64 | * @return FAR (fault address register) content (address that caused a page fault) |
62 | * @return FAR (fault address register) content (address that caused a page |
- | 63 | * fault) |
|
65 | */ |
64 | */ |
66 | static inline uintptr_t read_fault_address_register(void) |
65 | static inline uintptr_t read_fault_address_register(void) |
67 | { |
66 | { |
68 | uintptr_t ret; |
67 | uintptr_t ret; |
69 | 68 | ||
70 | // fault adress is stored in CP15 register 6 |
69 | /* fault adress is stored in CP15 register 6 */ |
71 | asm volatile ( |
70 | asm volatile ( |
72 | "mrc p15, 0, %0, c6, c0, 0" |
71 | "mrc p15, 0, %0, c6, c0, 0" |
73 | : "=r"(ret) |
72 | : "=r"(ret) |
74 | ); |
73 | ); |
75 | return ret; |
74 | return ret; |
76 | } |
75 | } |
77 | 76 | ||
78 | - | ||
79 | /** Decides whether the instruction is load/store or not. |
77 | /** Decides whether the instruction is load/store or not. |
80 | * |
78 | * |
81 | * @param instr Instruction |
79 | * @param instr Instruction |
82 | * |
80 | * |
83 | * @return true when instruction is load/store, false otherwise |
81 | * @return true when instruction is load/store, false otherwise |
84 | */ |
82 | */ |
85 | static inline bool is_load_store_instruction(instruction_t instr) |
83 | static inline bool is_load_store_instruction(instruction_t instr) |
86 | { |
84 | { |
87 | // load store immediate offset |
85 | /* load store immediate offset */ |
88 | if (instr.type == 0x2) { |
86 | if (instr.type == 0x2) { |
89 | return true; |
87 | return true; |
90 | } |
88 | } |
91 | 89 | ||
92 | // load store register offset |
90 | /* load store register offset */ |
93 | if (instr.type == 0x3 && instr.bit4 == 0) { |
91 | if (instr.type == 0x3 && instr.bit4 == 0) { |
94 | return true; |
92 | return true; |
95 | } |
93 | } |
96 | 94 | ||
97 | // load store multiple |
95 | /* load store multiple */ |
98 | if (instr.type == 0x4) { |
96 | if (instr.type == 0x4) { |
99 | return true; |
97 | return true; |
100 | } |
98 | } |
101 | 99 | ||
102 | // coprocessor load/store |
100 | /* oprocessor load/store */ |
103 | if (instr.type == 0x6) { |
101 | if (instr.type == 0x6) { |
104 | return true; |
102 | return true; |
105 | } |
103 | } |
106 | 104 | ||
107 | return false; |
105 | return false; |
108 | } |
106 | } |
109 | 107 | ||
110 | - | ||
111 | /** Decides whether the instructions is swap or not. |
108 | /** Decides whether the instruction is swap or not. |
112 | * |
109 | * |
113 | * @param instr Instruction |
110 | * @param instr Instruction |
114 | * |
111 | * |
115 | * @return true when instruction is swap, false otherwise |
112 | * @return true when instruction is swap, false otherwise |
116 | */ |
113 | */ |
117 | static inline bool is_swap_instruction(instruction_t instr) |
114 | static inline bool is_swap_instruction(instruction_t instr) |
118 | { |
115 | { |
119 | // swap, swapb instruction |
116 | /* swap, swapb instruction */ |
120 | if (instr.type == 0x0 && |
117 | if (instr.type == 0x0 && |
121 | (instr.opcode == 0x8 || instr.opcode == 0xa) && |
118 | (instr.opcode == 0x8 || instr.opcode == 0xa) && |
122 | instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) { |
119 | instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) { |
123 | return true; |
120 | return true; |
124 | } |
121 | } |
125 | 122 | ||
126 | return false; |
123 | return false; |
127 | } |
124 | } |
128 | 125 | ||
129 | - | ||
130 | /** Decides whether read or write into memory is requested. |
126 | /** Decides whether read or write into memory is requested. |
131 | * |
127 | * |
132 | * @param instr_addr Address of instruction which tries to access memory. |
128 | * @param instr_addr Address of instruction which tries to access memory. |
133 | * @param badvaddr Virtual address the instruction tries to access. |
129 | * @param badvaddr Virtual address the instruction tries to access. |
134 | * |
130 | * |
135 | * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is requested. |
131 | * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is |
- | 132 | * requested. |
|
136 | */ |
133 | */ |
137 | static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr) |
134 | static pf_access_t get_memory_access_type(uint32_t instr_addr, |
- | 135 | uintptr_t badvaddr) |
|
138 | { |
136 | { |
139 | instruction_union_t instr_union; |
137 | instruction_union_t instr_union; |
140 | instr_union.pc = instr_addr; |
138 | instr_union.pc = instr_addr; |
141 | 139 | ||
142 | instruction_t instr = *(instr_union.instr); |
140 | instruction_t instr = *(instr_union.instr); |
143 | 141 | ||
144 | // undefined instructions |
142 | /* undefined instructions */ |
145 | if (instr.condition == 0xf) { |
143 | if (instr.condition == 0xf) { |
146 | panic("page_fault - instruction doesn't access memory (instr_code: %x, badvaddr:%x)", |
144 | panic("page_fault - instruction doesn't access memory " |
147 | instr, badvaddr); |
145 | "(instr_code: %x, badvaddr:%x)", instr, badvaddr); |
148 | return PF_ACCESS_EXEC; |
146 | return PF_ACCESS_EXEC; |
149 | } |
147 | } |
150 | 148 | ||
151 | // load store instructions |
149 | /* load store instructions */ |
152 | if (is_load_store_instruction(instr)) { |
150 | if (is_load_store_instruction(instr)) { |
153 | if (instr.access == 1) { |
151 | if (instr.access == 1) { |
154 | return PF_ACCESS_READ; |
152 | return PF_ACCESS_READ; |
155 | } else { |
153 | } else { |
156 | return PF_ACCESS_WRITE; |
154 | return PF_ACCESS_WRITE; |
157 | } |
155 | } |
158 | } |
156 | } |
159 | 157 | ||
160 | // swap, swpb instruction |
158 | /* swap, swpb instruction */ |
161 | if (is_swap_instruction(instr)) { |
159 | if (is_swap_instruction(instr)) { |
162 | return PF_ACCESS_WRITE; |
160 | return PF_ACCESS_WRITE; |
163 | } |
161 | } |
164 | 162 | ||
165 | panic("page_fault - instruction doesn't access memory (instr_code: %x, badvaddr:%x)", |
163 | panic("page_fault - instruction doesn't access memory " |
166 | instr, badvaddr); |
164 | "(instr_code: %x, badvaddr:%x)", instr, badvaddr); |
167 | 165 | ||
168 | return PF_ACCESS_EXEC; |
166 | return PF_ACCESS_EXEC; |
169 | } |
167 | } |
170 | 168 | ||
171 | /** Handles "data abort" exception (load or store at invalid address). |
169 | /** Handles "data abort" exception (load or store at invalid address). |
172 | * |
170 | * |
173 | * @param exc_no Exception number. |
171 | * @param exc_no Exception number. |
174 | * @param istate CPU state when exception occured. |
172 | * @param istate CPU state when exception occured. |
175 | */ |
173 | */ |
176 | void data_abort(int exc_no, istate_t *istate) |
174 | void data_abort(int exc_no, istate_t *istate) |
177 | { |
175 | { |
178 | fault_status_t fsr = read_fault_status_register(); |
176 | fault_status_t fsr = read_fault_status_register(); |
179 | uintptr_t badvaddr = read_fault_address_register(); |
177 | uintptr_t badvaddr = read_fault_address_register(); |
180 | 178 | ||
181 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr); |
179 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr); |
182 | 180 | ||
183 | int ret = as_page_fault(badvaddr, access, istate); |
181 | int ret = as_page_fault(badvaddr, access, istate); |
184 | 182 | ||
185 | if (ret == AS_PF_FAULT) { |
183 | if (ret == AS_PF_FAULT) { |
186 | print_istate(istate); |
184 | print_istate(istate); |
187 | dprintf("page fault - pc: %x, va: %x, status: %x(%x), access:%d\n", |
185 | dprintf("page fault - pc: %x, va: %x, status: %x(%x), " |
188 | istate->pc, badvaddr, fsr.status, fsr, access); |
186 | "access:%d\n", istate->pc, badvaddr, fsr.status, fsr, |
- | 187 | access); |
|
189 | 188 | ||
190 | fault_if_from_uspace(istate, "Page fault: %#x", badvaddr); |
189 | fault_if_from_uspace(istate, "Page fault: %#x", badvaddr); |
191 | panic("page fault\n"); |
190 | panic("page fault\n"); |
192 | } |
191 | } |
193 | } |
192 | } |
194 | 193 | ||
195 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
194 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
196 | * |
195 | * |
197 | * @param exc_no Exception number. |
196 | * @param exc_no Exception number. |
198 | * @param istate CPU state when exception occured. |
197 | * @param istate CPU state when exception occured. |
199 | */ |
198 | */ |
200 | void prefetch_abort(int exc_no, istate_t *istate) |
199 | void prefetch_abort(int exc_no, istate_t *istate) |
201 | { |
200 | { |
202 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
201 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
203 | 202 | ||
204 | if (ret == AS_PF_FAULT) { |
203 | if (ret == AS_PF_FAULT) { |
205 | dprintf("prefetch_abort\n"); |
204 | dprintf("prefetch_abort\n"); |
206 | print_istate(istate); |
205 | print_istate(istate); |
207 | panic("page fault - prefetch_abort at address: %x\n", istate->pc); |
206 | panic("page fault - prefetch_abort at address: %x\n", |
- | 207 | istate->pc); |
|
208 | } |
208 | } |
209 | } |
209 | } |
210 | 210 | ||
211 | /** @} |
211 | /** @} |
212 | */ |
212 | */ |
213 | - | ||
214 | 213 |