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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * @brief Interrupts controlling routines. |
33 | * @brief Interrupts controlling routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <arch/asm.h> |
36 | #include <arch/asm.h> |
37 | #include <arch/regutils.h> |
37 | #include <arch/regutils.h> |
38 | #include <arch/machine.h> |
38 | #include <arch/machine.h> |
39 | #include <ddi/irq.h> |
39 | #include <ddi/irq.h> |
40 | #include <ddi/device.h> |
40 | #include <ddi/device.h> |
41 | #include <interrupt.h> |
41 | #include <interrupt.h> |
42 | 42 | ||
43 | /** Initial size of a table holding interrupt handlers. */ |
43 | /** Initial size of a table holding interrupt handlers. */ |
44 | #define IRQ_COUNT 8 |
44 | #define IRQ_COUNT 8 |
45 | 45 | ||
46 | /** Disable interrupts. |
46 | /** Disable interrupts. |
47 | * |
47 | * |
48 | * @return Old interrupt priority level. |
48 | * @return Old interrupt priority level. |
49 | */ |
49 | */ |
50 | ipl_t interrupts_disable(void) |
50 | ipl_t interrupts_disable(void) |
51 | { |
51 | { |
52 | ipl_t ipl = current_status_reg_read(); |
52 | ipl_t ipl = current_status_reg_read(); |
53 | 53 | ||
54 | current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl); |
54 | current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl); |
55 | 55 | ||
56 | return ipl; |
56 | return ipl; |
57 | } |
57 | } |
58 | 58 | ||
59 | /** Enable interrupts. |
59 | /** Enable interrupts. |
60 | * |
60 | * |
61 | * @return Old interrupt priority level. |
61 | * @return Old interrupt priority level. |
62 | */ |
62 | */ |
63 | ipl_t interrupts_enable(void) |
63 | ipl_t interrupts_enable(void) |
64 | { |
64 | { |
65 | ipl_t ipl = current_status_reg_read(); |
65 | ipl_t ipl = current_status_reg_read(); |
66 | 66 | ||
67 | /* |
67 | /* |
68 | * Current implementation of interrupt handling is non-nested mode. |
68 | * Current implementation of interrupt handling is non-nested mode. |
69 | * So we don't enable interrupt if servicing IRQ. |
69 | * So we don't enable interrupt if servicing IRQ. |
70 | * ToDo: Re-implement interrupt handling to handle nested interrupts. |
70 | * ToDo: Re-implement interrupt handling to handle nested interrupts. |
71 | */ |
71 | */ |
72 | if (!((ipl & 0x1b) == 0x1b)) |
72 | if ((ipl & 0x1f) != UNDEFINED_MODE) |
73 | current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT); |
73 | current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT); |
74 | 74 | ||
75 | return ipl; |
75 | return ipl; |
76 | } |
76 | } |
77 | 77 | ||
78 | /** Restore interrupt priority level. |
78 | /** Restore interrupt priority level. |
79 | * |
79 | * |
80 | * @param ipl Saved interrupt priority level. |
80 | * @param ipl Saved interrupt priority level. |
81 | */ |
81 | */ |
82 | void interrupts_restore(ipl_t ipl) |
82 | void interrupts_restore(ipl_t ipl) |
83 | { |
83 | { |
84 | current_status_reg_control_write( |
84 | current_status_reg_control_write( |
85 | (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) | |
85 | (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) | |
86 | (ipl & STATUS_REG_IRQ_DISABLED_BIT)); |
86 | (ipl & STATUS_REG_IRQ_DISABLED_BIT)); |
87 | } |
87 | } |
88 | 88 | ||
89 | /** Read interrupt priority level. |
89 | /** Read interrupt priority level. |
90 | * |
90 | * |
91 | * @return Current interrupt priority level. |
91 | * @return Current interrupt priority level. |
92 | */ |
92 | */ |
93 | ipl_t interrupts_read(void) |
93 | ipl_t interrupts_read(void) |
94 | { |
94 | { |
95 | return current_status_reg_read(); |
95 | return current_status_reg_read(); |
96 | } |
96 | } |
97 | 97 | ||
98 | /** Initialize basic tables for exception dispatching |
98 | /** Initialize basic tables for exception dispatching |
99 | * and starts the timer. |
99 | * and starts the timer. |
100 | */ |
100 | */ |
101 | void interrupt_init(void) |
101 | void interrupt_init(void) |
102 | { |
102 | { |
103 | irq_init(IRQ_COUNT, IRQ_COUNT); |
103 | irq_init(IRQ_COUNT, IRQ_COUNT); |
104 | machine_timer_irq_start(); |
104 | machine_timer_irq_start(); |
105 | 105 | ||
106 | } |
106 | } |
107 | 107 | ||
108 | /** @} |
108 | /** @} |
109 | */ |
109 | */ |
110 | 110 |