Rev 4647 | Rev 4665 | Go to most recent revision | Only display areas with differences | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 4647 | Rev 4651 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * @brief Exception handlers and exception initialization routines. |
33 | * @brief Exception handlers and exception initialization routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <arch/exception.h> |
36 | #include <arch/exception.h> |
37 | #include <arch/memstr.h> |
37 | #include <arch/memstr.h> |
38 | #include <arch/regutils.h> |
38 | #include <arch/regutils.h> |
39 | #include <interrupt.h> |
39 | #include <interrupt.h> |
40 | #include <arch/mm/page_fault.h> |
40 | #include <arch/mm/page_fault.h> |
41 | #include <arch/barrier.h> |
41 | #include <arch/barrier.h> |
42 | #include <arch/drivers/gxemul.h> |
42 | #include <arch/machine.h> |
43 | #include <print.h> |
43 | #include <print.h> |
44 | #include <syscall/syscall.h> |
44 | #include <syscall/syscall.h> |
45 | 45 | ||
46 | /** Offset used in calculation of exception handler's relative address. |
46 | /** Offset used in calculation of exception handler's relative address. |
47 | * |
47 | * |
48 | * @see install_handler() |
48 | * @see install_handler() |
49 | */ |
49 | */ |
50 | #define PREFETCH_OFFSET 0x8 |
50 | #define PREFETCH_OFFSET 0x8 |
51 | 51 | ||
52 | /** LDR instruction's code */ |
52 | /** LDR instruction's code */ |
53 | #define LDR_OPCODE 0xe59ff000 |
53 | #define LDR_OPCODE 0xe59ff000 |
54 | 54 | ||
55 | /** Number of exception vectors. */ |
55 | /** Number of exception vectors. */ |
56 | #define EXC_VECTORS 8 |
56 | #define EXC_VECTORS 8 |
57 | 57 | ||
58 | /** Size of memory block occupied by exception vectors. */ |
58 | /** Size of memory block occupied by exception vectors. */ |
59 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
59 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
60 | 60 | ||
61 | /** Switches to kernel stack and saves all registers there. |
61 | /** Switches to kernel stack and saves all registers there. |
62 | * |
62 | * |
63 | * Temporary exception stack is used to save a few registers |
63 | * Temporary exception stack is used to save a few registers |
64 | * before stack switch takes place. |
64 | * before stack switch takes place. |
65 | * |
65 | * |
66 | */ |
66 | */ |
67 | inline static void setup_stack_and_save_regs() |
67 | inline static void setup_stack_and_save_regs() |
68 | { |
68 | { |
69 | asm volatile ( |
69 | asm volatile ( |
70 | "ldr r13, =exc_stack\n" |
70 | "ldr r13, =exc_stack\n" |
71 | "stmfd r13!, {r0}\n" |
71 | "stmfd r13!, {r0}\n" |
72 | "mrs r0, spsr\n" |
72 | "mrs r0, spsr\n" |
73 | "and r0, r0, #0x1f\n" |
73 | "and r0, r0, #0x1f\n" |
74 | "cmp r0, #0x10\n" |
74 | "cmp r0, #0x10\n" |
75 | "bne 1f\n" |
75 | "bne 1f\n" |
76 | 76 | ||
77 | /* prev mode was usermode */ |
77 | /* prev mode was usermode */ |
78 | "ldmfd r13!, {r0}\n" |
78 | "ldmfd r13!, {r0}\n" |
79 | "ldr r13, =supervisor_sp\n" |
79 | "ldr r13, =supervisor_sp\n" |
80 | "ldr r13, [r13]\n" |
80 | "ldr r13, [r13]\n" |
81 | "stmfd r13!, {lr}\n" |
81 | "stmfd r13!, {lr}\n" |
82 | "stmfd r13!, {r0-r12}\n" |
82 | "stmfd r13!, {r0-r12}\n" |
83 | "stmfd r13!, {r13, lr}^\n" |
83 | "stmfd r13!, {r13, lr}^\n" |
84 | "mrs r0, spsr\n" |
84 | "mrs r0, spsr\n" |
85 | "stmfd r13!, {r0}\n" |
85 | "stmfd r13!, {r0}\n" |
86 | "b 2f\n" |
86 | "b 2f\n" |
87 | 87 | ||
88 | /* mode was not usermode */ |
88 | /* mode was not usermode */ |
89 | "1:\n" |
89 | "1:\n" |
90 | "stmfd r13!, {r1, r2, r3}\n" |
90 | "stmfd r13!, {r1, r2, r3}\n" |
91 | "mrs r1, cpsr\n" |
91 | "mrs r1, cpsr\n" |
92 | "mov r2, lr\n" |
92 | "mov r2, lr\n" |
93 | "bic r1, r1, #0x1f\n" |
93 | "bic r1, r1, #0x1f\n" |
94 | "orr r1, r1, r0\n" |
94 | "orr r1, r1, r0\n" |
95 | "mrs r0, cpsr\n" |
95 | "mrs r0, cpsr\n" |
96 | "msr cpsr_c, r1\n" |
96 | "msr cpsr_c, r1\n" |
97 | 97 | ||
98 | "mov r3, r13\n" |
98 | "mov r3, r13\n" |
99 | "stmfd r13!, {r2}\n" |
99 | "stmfd r13!, {r2}\n" |
100 | "mov r2, lr\n" |
100 | "mov r2, lr\n" |
101 | "stmfd r13!, {r4-r12}\n" |
101 | "stmfd r13!, {r4-r12}\n" |
102 | "mov r1, r13\n" |
102 | "mov r1, r13\n" |
103 | 103 | ||
104 | /* the following two lines are for debugging */ |
104 | /* the following two lines are for debugging */ |
105 | "mov sp, #0\n" |
105 | "mov sp, #0\n" |
106 | "mov lr, #0\n" |
106 | "mov lr, #0\n" |
107 | "msr cpsr_c, r0\n" |
107 | "msr cpsr_c, r0\n" |
108 | 108 | ||
109 | "ldmfd r13!, {r4, r5, r6, r7}\n" |
109 | "ldmfd r13!, {r4, r5, r6, r7}\n" |
110 | "stmfd r1!, {r4, r5, r6}\n" |
110 | "stmfd r1!, {r4, r5, r6}\n" |
111 | "stmfd r1!, {r7}\n" |
111 | "stmfd r1!, {r7}\n" |
112 | "stmfd r1!, {r2}\n" |
112 | "stmfd r1!, {r2}\n" |
113 | "stmfd r1!, {r3}\n" |
113 | "stmfd r1!, {r3}\n" |
114 | "mrs r0, spsr\n" |
114 | "mrs r0, spsr\n" |
115 | "stmfd r1!, {r0}\n" |
115 | "stmfd r1!, {r0}\n" |
116 | "mov r13, r1\n" |
116 | "mov r13, r1\n" |
117 | 117 | ||
118 | "2:\n" |
118 | "2:\n" |
119 | ); |
119 | ); |
120 | } |
120 | } |
121 | 121 | ||
122 | /** Returns from exception mode. |
122 | /** Returns from exception mode. |
123 | * |
123 | * |
124 | * Previously saved state of registers (including control register) |
124 | * Previously saved state of registers (including control register) |
125 | * is restored from the stack. |
125 | * is restored from the stack. |
126 | */ |
126 | */ |
127 | inline static void load_regs() |
127 | inline static void load_regs() |
128 | { |
128 | { |
129 | asm volatile( |
129 | asm volatile( |
130 | "ldmfd r13!, {r0} \n" |
130 | "ldmfd r13!, {r0} \n" |
131 | "msr spsr, r0 \n" |
131 | "msr spsr, r0 \n" |
132 | "and r0, r0, #0x1f \n" |
132 | "and r0, r0, #0x1f \n" |
133 | "cmp r0, #0x10 \n" |
133 | "cmp r0, #0x10 \n" |
134 | "bne 1f \n" |
134 | "bne 1f \n" |
135 | 135 | ||
136 | /* return to user mode */ |
136 | /* return to user mode */ |
137 | "ldmfd r13!, {r13, lr}^ \n" |
137 | "ldmfd r13!, {r13, lr}^ \n" |
138 | "b 2f \n" |
138 | "b 2f \n" |
139 | 139 | ||
140 | /* return to non-user mode */ |
140 | /* return to non-user mode */ |
141 | "1:\n" |
141 | "1:\n" |
142 | "ldmfd r13!, {r1, r2} \n" |
142 | "ldmfd r13!, {r1, r2} \n" |
143 | "mrs r3, cpsr \n" |
143 | "mrs r3, cpsr \n" |
144 | "bic r3, r3, #0x1f \n" |
144 | "bic r3, r3, #0x1f \n" |
145 | "orr r3, r3, r0 \n" |
145 | "orr r3, r3, r0 \n" |
146 | "mrs r0, cpsr \n" |
146 | "mrs r0, cpsr \n" |
147 | "msr cpsr_c, r3 \n" |
147 | "msr cpsr_c, r3 \n" |
148 | 148 | ||
149 | "mov r13, r1 \n" |
149 | "mov r13, r1 \n" |
150 | "mov lr, r2 \n" |
150 | "mov lr, r2 \n" |
151 | "msr cpsr_c, r0 \n" |
151 | "msr cpsr_c, r0 \n" |
152 | 152 | ||
153 | /* actual return */ |
153 | /* actual return */ |
154 | "2:\n" |
154 | "2:\n" |
155 | "ldmfd r13, {r0-r12, pc}^\n" |
155 | "ldmfd r13!, {r0-r12, pc}^\n" |
156 | ); |
156 | ); |
157 | } |
157 | } |
158 | 158 | ||
159 | 159 | ||
160 | /** Switch CPU to mode in which interrupts are serviced (currently it |
160 | /** Switch CPU to mode in which interrupts are serviced (currently it |
161 | * is Undefined mode). |
161 | * is Undefined mode). |
162 | * |
162 | * |
163 | * The default mode for interrupt servicing (Interrupt Mode) |
163 | * The default mode for interrupt servicing (Interrupt Mode) |
164 | * can not be used because of nested interrupts (which can occur |
164 | * can not be used because of nested interrupts (which can occur |
165 | * because interrupts are enabled in higher levels of interrupt handler). |
165 | * because interrupts are enabled in higher levels of interrupt handler). |
166 | */ |
166 | */ |
167 | inline static void switch_to_irq_servicing_mode() |
167 | inline static void switch_to_irq_servicing_mode() |
168 | { |
168 | { |
169 | /* switch to Undefined mode */ |
169 | /* switch to Undefined mode */ |
170 | asm volatile( |
170 | asm volatile( |
171 | /* save regs used during switching */ |
171 | /* save regs used during switching */ |
172 | "stmfd sp!, {r0-r3} \n" |
172 | "stmfd sp!, {r0-r3} \n" |
173 | 173 | ||
174 | /* save stack pointer and link register to r1, r2 */ |
174 | /* save stack pointer and link register to r1, r2 */ |
175 | "mov r1, sp \n" |
175 | "mov r1, sp \n" |
176 | "mov r2, lr \n" |
176 | "mov r2, lr \n" |
177 | 177 | ||
178 | /* mode switch */ |
178 | /* mode switch */ |
179 | "mrs r0, cpsr \n" |
179 | "mrs r0, cpsr \n" |
180 | "bic r0, r0, #0x1f \n" |
180 | "bic r0, r0, #0x1f \n" |
181 | "orr r0, r0, #0x1b \n" |
181 | "orr r0, r0, #0x1b \n" |
182 | "msr cpsr_c, r0 \n" |
182 | "msr cpsr_c, r0 \n" |
183 | 183 | ||
184 | /* restore saved sp and lr */ |
184 | /* restore saved sp and lr */ |
185 | "mov sp, r1 \n" |
185 | "mov sp, r1 \n" |
186 | "mov lr, r2 \n" |
186 | "mov lr, r2 \n" |
187 | 187 | ||
188 | /* restore original regs */ |
188 | /* restore original regs */ |
189 | "ldmfd sp!, {r0-r3} \n" |
189 | "ldmfd sp!, {r0-r3} \n" |
190 | ); |
190 | ); |
191 | } |
191 | } |
192 | 192 | ||
193 | /** Calls exception dispatch routine. */ |
193 | /** Calls exception dispatch routine. */ |
194 | #define CALL_EXC_DISPATCH(exception) \ |
194 | #define CALL_EXC_DISPATCH(exception) \ |
195 | asm volatile ( \ |
195 | asm volatile ( \ |
196 | "mov r0, %[exc]\n" \ |
196 | "mov r0, %[exc]\n" \ |
197 | "mov r1, r13\n" \ |
197 | "mov r1, r13\n" \ |
198 | "bl exc_dispatch\n" \ |
198 | "bl exc_dispatch\n" \ |
199 | :: [exc] "i" (exception) \ |
199 | :: [exc] "i" (exception) \ |
200 | );\ |
200 | );\ |
201 | 201 | ||
202 | /** General exception handler. |
202 | /** General exception handler. |
203 | * |
203 | * |
204 | * Stores registers, dispatches the exception, |
204 | * Stores registers, dispatches the exception, |
205 | * and finally restores registers and returns from exception processing. |
205 | * and finally restores registers and returns from exception processing. |
206 | * |
206 | * |
207 | * @param exception Exception number. |
207 | * @param exception Exception number. |
208 | */ |
208 | */ |
209 | #define PROCESS_EXCEPTION(exception) \ |
209 | #define PROCESS_EXCEPTION(exception) \ |
210 | setup_stack_and_save_regs(); \ |
210 | setup_stack_and_save_regs(); \ |
211 | CALL_EXC_DISPATCH(exception) \ |
211 | CALL_EXC_DISPATCH(exception) \ |
212 | load_regs(); |
212 | load_regs(); |
213 | 213 | ||
214 | /** Updates specified exception vector to jump to given handler. |
214 | /** Updates specified exception vector to jump to given handler. |
215 | * |
215 | * |
216 | * Addresses of handlers are stored in memory following exception vectors. |
216 | * Addresses of handlers are stored in memory following exception vectors. |
217 | */ |
217 | */ |
218 | static void install_handler(unsigned handler_addr, unsigned *vector) |
218 | static void install_handler(unsigned handler_addr, unsigned *vector) |
219 | { |
219 | { |
220 | /* relative address (related to exc. vector) of the word |
220 | /* relative address (related to exc. vector) of the word |
221 | * where handler's address is stored |
221 | * where handler's address is stored |
222 | */ |
222 | */ |
223 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - |
223 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - |
224 | PREFETCH_OFFSET; |
224 | PREFETCH_OFFSET; |
225 | 225 | ||
226 | /* make it LDR instruction and store at exception vector */ |
226 | /* make it LDR instruction and store at exception vector */ |
227 | *vector = handler_address_ptr | LDR_OPCODE; |
227 | *vector = handler_address_ptr | LDR_OPCODE; |
228 | smc_coherence(*vector); |
228 | smc_coherence(*vector); |
229 | 229 | ||
230 | /* store handler's address */ |
230 | /* store handler's address */ |
231 | *(vector + EXC_VECTORS) = handler_addr; |
231 | *(vector + EXC_VECTORS) = handler_addr; |
232 | 232 | ||
233 | } |
233 | } |
234 | 234 | ||
235 | /** Low-level Reset Exception handler. */ |
235 | /** Low-level Reset Exception handler. */ |
236 | static void reset_exception_entry(void) |
236 | static void reset_exception_entry(void) |
237 | { |
237 | { |
238 | PROCESS_EXCEPTION(EXC_RESET); |
238 | PROCESS_EXCEPTION(EXC_RESET); |
239 | } |
239 | } |
240 | 240 | ||
241 | /** Low-level Software Interrupt Exception handler. */ |
241 | /** Low-level Software Interrupt Exception handler. */ |
242 | static void swi_exception_entry(void) |
242 | static void swi_exception_entry(void) |
243 | { |
243 | { |
244 | PROCESS_EXCEPTION(EXC_SWI); |
244 | PROCESS_EXCEPTION(EXC_SWI); |
245 | } |
245 | } |
246 | 246 | ||
247 | /** Low-level Undefined Instruction Exception handler. */ |
247 | /** Low-level Undefined Instruction Exception handler. */ |
248 | static void undef_instr_exception_entry(void) |
248 | static void undef_instr_exception_entry(void) |
249 | { |
249 | { |
250 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
250 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
251 | } |
251 | } |
252 | 252 | ||
253 | /** Low-level Fast Interrupt Exception handler. */ |
253 | /** Low-level Fast Interrupt Exception handler. */ |
254 | static void fiq_exception_entry(void) |
254 | static void fiq_exception_entry(void) |
255 | { |
255 | { |
256 | PROCESS_EXCEPTION(EXC_FIQ); |
256 | PROCESS_EXCEPTION(EXC_FIQ); |
257 | } |
257 | } |
258 | 258 | ||
259 | /** Low-level Prefetch Abort Exception handler. */ |
259 | /** Low-level Prefetch Abort Exception handler. */ |
260 | static void prefetch_abort_exception_entry(void) |
260 | static void prefetch_abort_exception_entry(void) |
261 | { |
261 | { |
262 | asm volatile ( |
262 | asm volatile ( |
263 | "sub lr, lr, #4" |
263 | "sub lr, lr, #4" |
264 | ); |
264 | ); |
265 | 265 | ||
266 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
266 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
267 | } |
267 | } |
268 | 268 | ||
269 | /** Low-level Data Abort Exception handler. */ |
269 | /** Low-level Data Abort Exception handler. */ |
270 | static void data_abort_exception_entry(void) |
270 | static void data_abort_exception_entry(void) |
271 | { |
271 | { |
272 | asm volatile ( |
272 | asm volatile ( |
273 | "sub lr, lr, #8" |
273 | "sub lr, lr, #8" |
274 | ); |
274 | ); |
275 | 275 | ||
276 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
276 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
277 | } |
277 | } |
278 | 278 | ||
279 | /** Low-level Interrupt Exception handler. |
279 | /** Low-level Interrupt Exception handler. |
280 | * |
280 | * |
281 | * CPU is switched to Undefined mode before further interrupt processing |
281 | * CPU is switched to Undefined mode before further interrupt processing |
282 | * because of possible occurence of nested interrupt exception, which |
282 | * because of possible occurence of nested interrupt exception, which |
283 | * would overwrite (and thus spoil) stack pointer. |
283 | * would overwrite (and thus spoil) stack pointer. |
284 | */ |
284 | */ |
285 | static void irq_exception_entry(void) |
285 | static void irq_exception_entry(void) |
286 | { |
286 | { |
287 | asm volatile ( |
287 | asm volatile ( |
288 | "sub lr, lr, #4" |
288 | "sub lr, lr, #4" |
289 | ); |
289 | ); |
290 | 290 | ||
291 | setup_stack_and_save_regs(); |
291 | setup_stack_and_save_regs(); |
292 | 292 | ||
293 | switch_to_irq_servicing_mode(); |
293 | switch_to_irq_servicing_mode(); |
294 | 294 | ||
295 | CALL_EXC_DISPATCH(EXC_IRQ) |
295 | CALL_EXC_DISPATCH(EXC_IRQ) |
296 | 296 | ||
297 | load_regs(); |
297 | load_regs(); |
298 | } |
298 | } |
299 | 299 | ||
300 | /** Software Interrupt handler. |
300 | /** Software Interrupt handler. |
301 | * |
301 | * |
302 | * Dispatches the syscall. |
302 | * Dispatches the syscall. |
303 | */ |
303 | */ |
304 | static void swi_exception(int exc_no, istate_t *istate) |
304 | static void swi_exception(int exc_no, istate_t *istate) |
305 | { |
305 | { |
306 | istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2, |
306 | istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2, |
307 | istate->r3, istate->r4, istate->r5, istate->r6); |
307 | istate->r3, istate->r4, istate->r5, istate->r6); |
308 | } |
308 | } |
309 | 309 | ||
310 | /** Returns the mask of active interrupts. */ |
- | |
311 | static inline uint32_t gxemul_irqc_get_sources(void) |
- | |
312 | { |
- | |
313 | return *((uint32_t *) gxemul_irqc); |
- | |
314 | } |
- | |
315 | - | ||
316 | /** Interrupt Exception handler. |
- | |
317 | * |
- | |
318 | * Determines the sources of interrupt and calls their handlers. |
- | |
319 | */ |
- | |
320 | static void irq_exception(int exc_no, istate_t *istate) |
- | |
321 | { |
- | |
322 | uint32_t sources = gxemul_irqc_get_sources(); |
- | |
323 | unsigned int i; |
- | |
324 | - | ||
325 | for (i = 0; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
- | |
326 | if (sources & (1 << i)) { |
- | |
327 | irq_t *irq = irq_dispatch_and_lock(i); |
- | |
328 | if (irq) { |
- | |
329 | /* The IRQ handler was found. */ |
- | |
330 | irq->handler(irq); |
- | |
331 | spinlock_unlock(&irq->lock); |
- | |
332 | } else { |
- | |
333 | /* Spurious interrupt.*/ |
- | |
334 | printf("cpu%d: spurious interrupt (inum=%d)\n", |
- | |
335 | CPU->id, i); |
- | |
336 | } |
- | |
337 | } |
- | |
338 | } |
- | |
339 | } |
- | |
340 | - | ||
341 | /** Fills exception vectors with appropriate exception handlers. */ |
310 | /** Fills exception vectors with appropriate exception handlers. */ |
342 | void install_exception_handlers(void) |
311 | void install_exception_handlers(void) |
343 | { |
312 | { |
344 | install_handler((unsigned) reset_exception_entry, |
313 | install_handler((unsigned) reset_exception_entry, |
345 | (unsigned *) EXC_RESET_VEC); |
314 | (unsigned *) EXC_RESET_VEC); |
346 | 315 | ||
347 | install_handler((unsigned) undef_instr_exception_entry, |
316 | install_handler((unsigned) undef_instr_exception_entry, |
348 | (unsigned *) EXC_UNDEF_INSTR_VEC); |
317 | (unsigned *) EXC_UNDEF_INSTR_VEC); |
349 | 318 | ||
350 | install_handler((unsigned) swi_exception_entry, |
319 | install_handler((unsigned) swi_exception_entry, |
351 | (unsigned *) EXC_SWI_VEC); |
320 | (unsigned *) EXC_SWI_VEC); |
352 | 321 | ||
353 | install_handler((unsigned) prefetch_abort_exception_entry, |
322 | install_handler((unsigned) prefetch_abort_exception_entry, |
354 | (unsigned *) EXC_PREFETCH_ABORT_VEC); |
323 | (unsigned *) EXC_PREFETCH_ABORT_VEC); |
355 | 324 | ||
356 | install_handler((unsigned) data_abort_exception_entry, |
325 | install_handler((unsigned) data_abort_exception_entry, |
357 | (unsigned *) EXC_DATA_ABORT_VEC); |
326 | (unsigned *) EXC_DATA_ABORT_VEC); |
358 | 327 | ||
359 | install_handler((unsigned) irq_exception_entry, |
328 | install_handler((unsigned) irq_exception_entry, |
360 | (unsigned *) EXC_IRQ_VEC); |
329 | (unsigned *) EXC_IRQ_VEC); |
361 | 330 | ||
362 | install_handler((unsigned) fiq_exception_entry, |
331 | install_handler((unsigned) fiq_exception_entry, |
363 | (unsigned *) EXC_FIQ_VEC); |
332 | (unsigned *) EXC_FIQ_VEC); |
364 | } |
333 | } |
365 | 334 | ||
366 | #ifdef HIGH_EXCEPTION_VECTORS |
335 | #ifdef HIGH_EXCEPTION_VECTORS |
367 | /** Activates use of high exception vectors addresses. */ |
336 | /** Activates use of high exception vectors addresses. */ |
368 | static void high_vectors(void) |
337 | static void high_vectors(void) |
369 | { |
338 | { |
370 | uint32_t control_reg; |
339 | uint32_t control_reg; |
371 | 340 | ||
372 | asm volatile ( |
341 | asm volatile ( |
373 | "mrc p15, 0, %[control_reg], c1, c1" |
342 | "mrc p15, 0, %[control_reg], c1, c1" |
374 | : [control_reg] "=r" (control_reg) |
343 | : [control_reg] "=r" (control_reg) |
375 | ); |
344 | ); |
376 | 345 | ||
377 | /* switch on the high vectors bit */ |
346 | /* switch on the high vectors bit */ |
378 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
347 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
379 | 348 | ||
380 | asm volatile ( |
349 | asm volatile ( |
381 | "mcr p15, 0, %[control_reg], c1, c1" |
350 | "mcr p15, 0, %[control_reg], c1, c1" |
382 | :: [control_reg] "r" (control_reg) |
351 | :: [control_reg] "r" (control_reg) |
383 | ); |
352 | ); |
384 | } |
353 | } |
385 | #endif |
354 | #endif |
386 | 355 | ||
- | 356 | /** Interrupt Exception handler. |
|
- | 357 | * |
|
- | 358 | * Determines the sources of interrupt and calls their handlers. |
|
- | 359 | */ |
|
- | 360 | static void irq_exception(int exc_no, istate_t *istate) |
|
- | 361 | { |
|
- | 362 | machine_irq_exception(exc_no, istate); |
|
- | 363 | } |
|
- | 364 | ||
387 | /** Initializes exception handling. |
365 | /** Initializes exception handling. |
388 | * |
366 | * |
389 | * Installs low-level exception handlers and then registers |
367 | * Installs low-level exception handlers and then registers |
390 | * exceptions and their handlers to kernel exception dispatcher. |
368 | * exceptions and their handlers to kernel exception dispatcher. |
391 | */ |
369 | */ |
392 | void exception_init(void) |
370 | void exception_init(void) |
393 | { |
371 | { |
394 | #ifdef HIGH_EXCEPTION_VECTORS |
372 | #ifdef HIGH_EXCEPTION_VECTORS |
395 | high_vectors(); |
373 | high_vectors(); |
396 | #endif |
374 | #endif |
397 | install_exception_handlers(); |
375 | install_exception_handlers(); |
398 | 376 | ||
399 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
377 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
400 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", |
378 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", |
401 | (iroutine) prefetch_abort); |
379 | (iroutine) prefetch_abort); |
402 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
380 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
403 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
381 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
404 | } |
382 | } |
405 | 383 | ||
406 | /** Prints #istate_t structure content. |
384 | /** Prints #istate_t structure content. |
407 | * |
385 | * |
408 | * @param istate Structure to be printed. |
386 | * @param istate Structure to be printed. |
409 | */ |
387 | */ |
410 | void print_istate(istate_t *istate) |
388 | void print_istate(istate_t *istate) |
411 | { |
389 | { |
412 | printf("istate dump:\n"); |
390 | printf("istate dump:\n"); |
413 | 391 | ||
414 | printf(" r0: %x r1: %x r2: %x r3: %x\n", |
392 | printf(" r0: %x r1: %x r2: %x r3: %x\n", |
415 | istate->r0, istate->r1, istate->r2, istate->r3); |
393 | istate->r0, istate->r1, istate->r2, istate->r3); |
416 | printf(" r4: %x r5: %x r6: %x r7: %x\n", |
394 | printf(" r4: %x r5: %x r6: %x r7: %x\n", |
417 | istate->r4, istate->r5, istate->r6, istate->r7); |
395 | istate->r4, istate->r5, istate->r6, istate->r7); |
418 | printf(" r8: %x r8: %x r10: %x r11: %x\n", |
396 | printf(" r8: %x r8: %x r10: %x r11: %x\n", |
419 | istate->r8, istate->r9, istate->r10, istate->r11); |
397 | istate->r8, istate->r9, istate->r10, istate->r11); |
420 | printf(" r12: %x sp: %x lr: %x spsr: %x\n", |
398 | printf(" r12: %x sp: %x lr: %x spsr: %x\n", |
421 | istate->r12, istate->sp, istate->lr, istate->spsr); |
399 | istate->r12, istate->sp, istate->lr, istate->spsr); |
422 | 400 | ||
423 | printf(" pc: %x\n", istate->pc); |
401 | printf(" pc: %x\n", istate->pc); |
424 | } |
402 | } |
425 | 403 | ||
426 | /** @} |
404 | /** @} |
427 | */ |
405 | */ |
428 | 406 |