WebSVN – HelenOS – Diff – /branches/arm/kernel/arch/arm32/src/exception.c


/*
 * Copyright (c) 2007 Petr Stepan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
    @brief  Exception handlers and exception initialization routines.
 */
 
 
#include <arch/exception.h>
#include <arch/debug/print.h>
#include <arch/memstr.h>
#include <arch/regutils.h>
#include <interrupt.h>
#include <arch/machine.h>
#include <arch/mm/page_fault.h>
#include <print.h>
#include <syscall/syscall.h>
 
/** Offset used in calculation of exception handler's relative address.
 *
 * @see install_handler()
 */
#define PREFETCH_OFFSET      0x8
 
/** LDR instruction's code */
#define LDR_OPCODE           0xe59ff000
 
/** Number of exception vectors. */
#define EXC_VECTORS          8
 
/** Size of memory block occupied by exception vectors. */
#define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
 
 
/** Kernel stack pointer.
 *
 * It is set when thread switches to user mode,
 * and then used for exception handling.
 */
extern uintptr_t supervisor_sp;
 
/** Temporary exception stack pointer.
 *
 * Temporary stack is used in exceptions handling routines
 * before switching to thread's kernel stack.
 */
extern uintptr_t exc_stack;
 
 
/** Switches to kernel stack and saves all registers there.
 *
 * Temporary exception stack is used to save a few registers
 * before stack switch takes place.
 */
inline static void setup_stack_and_save_regs()
{
asm volatile("ldr r13, =exc_stack       \n\
    stmfd r13!, {r0}            \n\
    mrs r0, spsr                \n\
    and r0, r0, #0x1f           \n\
    cmp r0, #0x10               \n\
    bne 1f                  \n\
                        \n\
    @prev mode was usermode         \n\
    ldmfd r13!, {r0}            \n\
    ldr r13, =supervisor_sp         \n\
    ldr r13, [r13]              \n\
    stmfd r13!, {lr}            \n\
    stmfd r13!, {r0-r12}            \n\
    stmfd r13!, {r13, lr}^          \n\
    mrs r0, spsr                \n\
    stmfd r13!, {r0}            \n\
    b 2f                    \n\
                        \n\
    @prev mode was not usermode     \n\
1:                      \n\
    stmfd r13!, {r1, r2, r3}        \n\
    mrs r1, cpsr                \n\
    mov r2, lr              \n\
    bic r1, r1, #0x1f           \n\
    orr r1, r1, r0              \n\
    mrs r0, cpsr                \n\
    msr cpsr_c, r1              \n\
                        \n\
    mov r3, r13             \n\
    stmfd r13!, {r2}            \n\
    mov r2, lr              \n\
    stmfd r13!, {r4-r12}            \n\
    mov r1, r13             \n\
    @following two lines are for debugging  \n\
    mov sp, #0              \n\
    mov lr, #0              \n\
    msr cpsr_c, r0              \n\
                        \n\
    ldmfd r13!, {r4, r5, r6, r7}        \n\
    stmfd r1!, {r4, r5, r6}         \n\
    stmfd r1!, {r7}             \n\
    stmfd r1!, {r2}             \n\
    stmfd r1!, {r3}             \n\
    mrs r0, spsr                \n\
    stmfd r1!, {r0}             \n\
    mov r13, r1             \n\
2:"
);
}
 
 
/** Returns from exception mode.
 *
 * Previously saved state of registers (including control register)
 * is restored from the stack.
 */
inline static void load_regs()
{
asm volatile(   "ldmfd r13!, {r0}       \n\
    msr spsr, r0                \n\
    and r0, r0, #0x1f           \n\
    cmp r0, #0x10               \n\
    bne 3f                  \n\
                        \n\
    @return to user mode            \n\
    ldmfd r13!, {r13, lr}^          \n\
    b 4f                    \n\
                        \n\
    @return to non-user mode        \n\
3:                      \n\
    ldmfd r13!, {r1, r2}            \n\
    mrs r3, cpsr                \n\
    bic r3, r3, #0x1f           \n\
    orr r3, r3, r0              \n\
    mrs r0, cpsr                \n\
    msr cpsr_c, r3              \n\
                        \n\
    mov r13, r1             \n\
    mov lr, r2              \n\
    msr cpsr_c, r0              \n\
                        \n\
    @actual return              \n\
4:  ldmfd r13, {r0-r12, pc}^"
);
}
 
/** Switch CPU to mode in which interrupts are serviced (currently it
 * is Undefined mode).
 *
 * The default mode for interrupt servicing (Interrupt Mode)
 * can not be used because of nested interrupts (which can occur
 * because interrupt are enabled in higher levels of interrupt handler).
 */
inline static void switchToIrqServicingMode()
{
    /* switch to Undefined mode */
    asm volatile(
        /* save regs used during switching */
        "stmfd sp!, {r0-r3}     \n"
 
        /* save stack pointer and link register to r1, r2 */
        "mov r1, sp         \n"
        "mov r2, lr         \n"
 
        /* mode switch */
        "mrs r0, cpsr           \n"
        "bic r0, r0, #0x1f      \n"
        "orr r0, r0, #0x1b      \n"
        "msr cpsr_c, r0         \n"
 
        /* restore saved sp and lr */
        "mov sp, r1         \n"
        "mov lr, r2         \n"
 
        /* restore original regs */
        "ldmfd sp!, {r0-r3}     \n"
    );
}
 
/** Calls exception dispatch routine. */
#define CALL_EXC_DISPATCH(exception)        \
    asm("mov r0, %0" : : "i" (exception));  \
    asm("mov r1, r13");         \
    asm("bl exc_dispatch");     
 
 
/** General exception handler.
 *
 *  Stores registers, dispatches the exception,
 *  and finally restores registers and returns from exception processing.
 *
 *  @param exception Exception number.
 */
#define PROCESS_EXCEPTION(exception)        \
    setup_stack_and_save_regs();        \
    CALL_EXC_DISPATCH(exception)        \
    load_regs();
 
 
/** Updates specified exception vector to jump to given handler.
 *
 *  Addresses of handlers are stored in memory following exception vectors.
 */
static void install_handler (unsigned handler_addr, unsigned* vector)
{
    /* relative address (related to exc. vector) of the word
     * where handler's address is stored
    */
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
   
    /* make it LDR instruction and store at exception vector */
    *vector = handler_address_ptr | LDR_OPCODE;
   
    /* store handler's address */
    *(vector + EXC_VECTORS) = handler_addr;
 
}
 
 
/** Low-level Reset Exception handler. */
static void reset_exception_entry()
{
    PROCESS_EXCEPTION(EXC_RESET);
}
 
 
/** Low-level Software Interrupt Exception handler. */
static void swi_exception_entry()
{
    PROCESS_EXCEPTION(EXC_SWI);
}
 
 
/** Low-level Undefined Instruction Exception handler. */
static void undef_instr_exception_entry()
{
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
}
 
 
/** Low-level Fast Interrupt Exception handler. */
static void fiq_exception_entry()
{
    PROCESS_EXCEPTION(EXC_FIQ);
}
 
 
/** Low-level Prefetch Abort Exception handler. */
static void prefetch_abort_exception_entry()
{
    asm("sub lr, lr, #4");
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
}
 
 
/** Low-level Data Abort Exception handler. */
static void data_abort_exception_entry()
{
    asm("sub lr, lr, #8");
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
}
 
 
/** Low-level Interrupt Exception handler.
 *
 * CPU is switched to Undefined mode before further interrupt processing
 * because of possible occurence of nested interrupt exception, which
 * would overwrite (and thus spoil) stack pointer.
 */
static void irq_exception_entry()
{
    asm("sub lr, lr, #4");
    setup_stack_and_save_regs();
   
    switchToIrqServicingMode();
 
 
 
 
 
 
 
 
 
 
   
    CALL_EXC_DISPATCH(EXC_IRQ)
 
    load_regs();
}
 
 
/** Software Interrupt handler.
 *
 * Dispatches the syscall.
 */
static void swi_exception(int exc_no, istate_t *istate)
{
    /*
    dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,
        istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);
    */
 
    istate->r0 = syscall_handler(
        istate->r0,
        istate->r1,
        istate->r2,
        istate->r3,
        istate->r4);
}
 
 
/** Interrupt Exception handler.
 *
 * Determines the sources of interrupt, and calls their handlers.
 */
static void irq_exception(int exc_no, istate_t *istate)
{
    machine_irq_exception(exc_no, istate);
}
 
 
/** Fills exception vectors with appropriate exception handlers. */
void install_exception_handlers(void)
{
    install_handler((unsigned)reset_exception_entry,
             (unsigned*)EXC_RESET_VEC);
   
    install_handler((unsigned)undef_instr_exception_entry,
             (unsigned*)EXC_UNDEF_INSTR_VEC);
   
    install_handler((unsigned)swi_exception_entry,
             (unsigned*)EXC_SWI_VEC);
   
    install_handler((unsigned)prefetch_abort_exception_entry,
             (unsigned*)EXC_PREFETCH_ABORT_VEC);
   
    install_handler((unsigned)data_abort_exception_entry,
             (unsigned*)EXC_DATA_ABORT_VEC);
   
    install_handler((unsigned)irq_exception_entry,
             (unsigned*)EXC_IRQ_VEC);
   
    install_handler((unsigned)fiq_exception_entry,
             (unsigned*)EXC_FIQ_VEC);
}
 
 
#ifdef HIGH_EXCEPTION_VECTORS
/** Activates use of high exception vectors addresses. */
static void high_vectors()
{
    uint32_t control_reg;
   
    asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
   
    //switch on the high vectors bit
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
   
    asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
}
#endif
 
 
/** Initializes exception handling.
 *
 * Installs low-level exception handlers and then registers
 * exceptions and their handlers to kernel exception dispatcher.
 */
void exception_init(void)
{
#ifdef HIGH_EXCEPTION_VECTORS
    high_vectors();
#endif
    install_exception_handlers();
   
    exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
    exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
    exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
    exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
}
 
 
/** Prints #istate_t structure content.
 *
 * @param istate Structure to be printed.
 */
void print_istate(istate_t *istate)
{
    dprintf("istate dump:\n");
 
    dprintf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
        istate->r0, istate->r1, istate->r2, istate->r3);
    dprintf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
        istate->r4, istate->r5, istate->r6, istate->r7);
    dprintf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
        istate->r8, istate->r9, istate->r10, istate->r11);
    dprintf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
        istate->r12, istate->sp, istate->lr, istate->spsr);
 
    dprintf(" pc: %x\n", istate->pc);
}
 
 
/** @}
 */
 

Rev 2355	Rev 2407
1	/*	1	/*
2	* Copyright (c) 2007 Petr Stepan	2	* Copyright (c) 2007 Petr Stepan
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	@brief Exception handlers and exception initialization routines.	33	@brief Exception handlers and exception initialization routines.
34	*/	34	*/
35		35
36		36
37	#include <arch/exception.h>	37	#include <arch/exception.h>
38	#include <arch/debug/print.h>	38	#include <arch/debug/print.h>
39	#include <arch/memstr.h>	39	#include <arch/memstr.h>
40	#include <arch/regutils.h>	40	#include <arch/regutils.h>
41	#include <interrupt.h>	41	#include <interrupt.h>
42	#include <arch/machine.h>	42	#include <arch/machine.h>
43	#include <arch/mm/page_fault.h>	43	#include <arch/mm/page_fault.h>
44	#include <print.h>	44	#include <print.h>
45	#include <syscall/syscall.h>	45	#include <syscall/syscall.h>
46		46
-		47	/** Offset used in calculation of exception handler's relative address.
47		48	*
-		49	* @see install_handler()
-		50	*/
48	#define PREFETCH_OFFSET 0x8	51	#define PREFETCH_OFFSET 0x8
-		52
49	#define BRANCH_OPCODE 0xea000000	53	/** LDR instruction's code */
50	#define LDR_OPCODE 0xe59ff000	54	#define LDR_OPCODE 0xe59ff000
-		55
51	#define VALID_BRANCH_MASK 0xff000000	56	/** Number of exception vectors. */
52	#define EXC_VECTORS_SIZE 0x20	57	#define EXC_VECTORS 8
-		58
-		59	/** Size of memory block occupied by exception vectors. */
53	#define EXC_VECTORS 0x8	60	#define EXC_VECTORS_SIZE (EXC_VECTORS * 4)
54		61
55		62
-		63	/** Kernel stack pointer.
-		64	*
-		65	* It is set when thread switches to user mode,
-		66	* and then used for exception handling.
-		67	*/
56	extern uintptr_t supervisor_sp;	68	extern uintptr_t supervisor_sp;
-		69
-		70	/** Temporary exception stack pointer.
-		71	*
-		72	* Temporary stack is used in exceptions handling routines
-		73	* before switching to thread's kernel stack.
-		74	*/
57	extern uintptr_t exc_stack;	75	extern uintptr_t exc_stack;
58		76
-		77
59	/** Switches to kernel stack and saves all registers there.	78	/** Switches to kernel stack and saves all registers there.
60	*	79	*
61	* Temporary exception stack is used to save a few registers	80	* Temporary exception stack is used to save a few registers
62	* before stack switch takes place.	81	* before stack switch takes place.
63	*/	82	*/
64	inline static void setup_stack_and_save_regs()	83	inline static void setup_stack_and_save_regs()
65	{	84	{
66	asm volatile("ldr r13, =exc_stack \n\	85	asm volatile("ldr r13, =exc_stack \n\
67	stmfd r13!, {r0} \n\	86	stmfd r13!, {r0} \n\
68	mrs r0, spsr \n\	87	mrs r0, spsr \n\
69	and r0, r0, #0x1f \n\	88	and r0, r0, #0x1f \n\
70	cmp r0, #0x10 \n\	89	cmp r0, #0x10 \n\
71	bne 1f \n\	90	bne 1f \n\
72	\n\	91	\n\
73	@prev mode was usermode \n\	92	@prev mode was usermode \n\
74	ldmfd r13!, {r0} \n\	93	ldmfd r13!, {r0} \n\
75	ldr r13, =supervisor_sp \n\	94	ldr r13, =supervisor_sp \n\
76	ldr r13, [r13] \n\	95	ldr r13, [r13] \n\
77	stmfd r13!, {lr} \n\	96	stmfd r13!, {lr} \n\
78	stmfd r13!, {r0-r12} \n\	97	stmfd r13!, {r0-r12} \n\
79	stmfd r13!, {r13, lr}^ \n\	98	stmfd r13!, {r13, lr}^ \n\
80	mrs r0, spsr \n\	99	mrs r0, spsr \n\
81	stmfd r13!, {r0} \n\	100	stmfd r13!, {r0} \n\
82	b 2f \n\	101	b 2f \n\
83	\n\	102	\n\
84	@prev mode was not usermode \n\	103	@prev mode was not usermode \n\
85	1: \n\	104	1: \n\
86	stmfd r13!, {r1, r2, r3} \n\	105	stmfd r13!, {r1, r2, r3} \n\
87	mrs r1, cpsr \n\	106	mrs r1, cpsr \n\
88	mov r2, lr \n\	107	mov r2, lr \n\
89	bic r1, r1, #0x1f \n\	108	bic r1, r1, #0x1f \n\
90	orr r1, r1, r0 \n\	109	orr r1, r1, r0 \n\
91	mrs r0, cpsr \n\	110	mrs r0, cpsr \n\
92	msr cpsr_c, r1 \n\	111	msr cpsr_c, r1 \n\
93	\n\	112	\n\
94	mov r3, r13 \n\	113	mov r3, r13 \n\
95	stmfd r13!, {r2} \n\	114	stmfd r13!, {r2} \n\
96	mov r2, lr \n\	115	mov r2, lr \n\
97	stmfd r13!, {r4-r12} \n\	116	stmfd r13!, {r4-r12} \n\
98	mov r1, r13 \n\	117	mov r1, r13 \n\
99	@following two lines are for debugging \n\	118	@following two lines are for debugging \n\
100	mov sp, #0 \n\	119	mov sp, #0 \n\
101	mov lr, #0 \n\	120	mov lr, #0 \n\
102	msr cpsr_c, r0 \n\	121	msr cpsr_c, r0 \n\
103	\n\	122	\n\
104	ldmfd r13!, {r4, r5, r6, r7} \n\	123	ldmfd r13!, {r4, r5, r6, r7} \n\
105	stmfd r1!, {r4, r5, r6} \n\	124	stmfd r1!, {r4, r5, r6} \n\
106	stmfd r1!, {r7} \n\	125	stmfd r1!, {r7} \n\
107	stmfd r1!, {r2} \n\	126	stmfd r1!, {r2} \n\
108	stmfd r1!, {r3} \n\	127	stmfd r1!, {r3} \n\
109	mrs r0, spsr \n\	128	mrs r0, spsr \n\
110	stmfd r1!, {r0} \n\	129	stmfd r1!, {r0} \n\
111	mov r13, r1 \n\	130	mov r13, r1 \n\
112	2:"	131	2:"
113	);	132	);
114	}	133	}
115		134
-		135
116	/** Returns from exception mode.	136	/** Returns from exception mode.
117	*	137	*
118	* Previously saved state of registers (including control register)	138	* Previously saved state of registers (including control register)
119	* is restored from the stack.	139	* is restored from the stack.
120	*/	140	*/
121	inline static void load_regs()	141	inline static void load_regs()
122	{	142	{
123	asm volatile( "ldmfd r13!, {r0} \n\	143	asm volatile( "ldmfd r13!, {r0} \n\
124	msr spsr, r0 \n\	144	msr spsr, r0 \n\
125	and r0, r0, #0x1f \n\	145	and r0, r0, #0x1f \n\
126	cmp r0, #0x10 \n\	146	cmp r0, #0x10 \n\
127	bne 3f \n\	147	bne 3f \n\
128	\n\	148	\n\
129	@return to user mode \n\	149	@return to user mode \n\
130	ldmfd r13!, {r13, lr}^ \n\	150	ldmfd r13!, {r13, lr}^ \n\
131	b 4f \n\	151	b 4f \n\
132	\n\	152	\n\
133	@return to non-user mode \n\	153	@return to non-user mode \n\
134	3: \n\	154	3: \n\
135	ldmfd r13!, {r1, r2} \n\	155	ldmfd r13!, {r1, r2} \n\
136	mrs r3, cpsr \n\	156	mrs r3, cpsr \n\
137	bic r3, r3, #0x1f \n\	157	bic r3, r3, #0x1f \n\
138	orr r3, r3, r0 \n\	158	orr r3, r3, r0 \n\
139	mrs r0, cpsr \n\	159	mrs r0, cpsr \n\
140	msr cpsr_c, r3 \n\	160	msr cpsr_c, r3 \n\
141	\n\	161	\n\
142	mov r13, r1 \n\	162	mov r13, r1 \n\
143	mov lr, r2 \n\	163	mov lr, r2 \n\
144	msr cpsr_c, r0 \n\	164	msr cpsr_c, r0 \n\
145	\n\	165	\n\
146	@actual return \n\	166	@actual return \n\
147	4: ldmfd r13, {r0-r12, pc}^"	167	4: ldmfd r13, {r0-r12, pc}^"
148	);	168	);
149	}	169	}
150		170
-		171	/** Switch CPU to mode in which interrupts are serviced (currently it
-		172	* is Undefined mode).
-		173	*
-		174	* The default mode for interrupt servicing (Interrupt Mode)
-		175	* can not be used because of nested interrupts (which can occur
-		176	* because interrupt are enabled in higher levels of interrupt handler).
-		177	*/
-		178	inline static void switchToIrqServicingMode()
-		179	{
-		180	/* switch to Undefined mode */
-		181	asm volatile(
-		182	/* save regs used during switching */
-		183	"stmfd sp!, {r0-r3} \n"
-		184
-		185	/* save stack pointer and link register to r1, r2 */
-		186	"mov r1, sp \n"
-		187	"mov r2, lr \n"
-		188
-		189	/* mode switch */
-		190	"mrs r0, cpsr \n"
-		191	"bic r0, r0, #0x1f \n"
-		192	"orr r0, r0, #0x1b \n"
-		193	"msr cpsr_c, r0 \n"
-		194
-		195	/* restore saved sp and lr */
-		196	"mov sp, r1 \n"
-		197	"mov lr, r2 \n"
-		198
-		199	/* restore original regs */
-		200	"ldmfd sp!, {r0-r3} \n"
-		201	);
-		202	}
-		203
151	/** Calls exception dispatch routine. */	204	/** Calls exception dispatch routine. */
152	#define CALL_EXC_DISPATCH(exception) \	205	#define CALL_EXC_DISPATCH(exception) \
153	asm("mov r0, %0" : : "i" (exception)); \	206	asm("mov r0, %0" : : "i" (exception)); \
154	asm("mov r1, r13"); \	207	asm("mov r1, r13"); \
155	asm("bl exc_dispatch");	208	asm("bl exc_dispatch");
156		209
157		210
158	/** General exception handler.	211	/** General exception handler.
159	*	212	*
160	* Stores registers, dispatches the exception,	213	* Stores registers, dispatches the exception,
161	* and finally restores registers and returns from exception processing.	214	* and finally restores registers and returns from exception processing.
162	*	215	*
163	* @param exception Exception number.	216	* @param exception Exception number.
164	*/	217	*/
165	#define PROCESS_EXCEPTION(exception) \	218	#define PROCESS_EXCEPTION(exception) \
166	setup_stack_and_save_regs(); \	219	setup_stack_and_save_regs(); \
167	CALL_EXC_DISPATCH(exception) \	220	CALL_EXC_DISPATCH(exception) \
168	load_regs();	221	load_regs();
169		222
170		223
171	/** Updates specified exception vector to jump to given handler.	224	/** Updates specified exception vector to jump to given handler.
172	*	225	*
173	* Addresses of handlers are stored in memory following exception vectors.	226	* Addresses of handlers are stored in memory following exception vectors.
174	*/	227	*/
175	static void install_handler (unsigned handler_addr, unsigned* vector)	228	static void install_handler (unsigned handler_addr, unsigned* vector)
176	{	229	{
177	/* relative address (related to exc. vector) of the word	230	/* relative address (related to exc. vector) of the word
178	* where handler's address is stored	231	* where handler's address is stored
179	*/	232	*/
180	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;	233	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
181		234
182	/* make it LDR instruction and store at exception vector */	235	/* make it LDR instruction and store at exception vector */
183	*vector = handler_address_ptr \| LDR_OPCODE;	236	*vector = handler_address_ptr \| LDR_OPCODE;
184		237
185	/* store handler's address */	238	/* store handler's address */
186	*(vector + EXC_VECTORS) = handler_addr;	239	*(vector + EXC_VECTORS) = handler_addr;
187		240
188	}	241	}
189		242
190		243
191	/** Low-level Reset Exception handler. */	244	/** Low-level Reset Exception handler. */
192	static void reset_exception_entry()	245	static void reset_exception_entry()
193	{	246	{
194	PROCESS_EXCEPTION(EXC_RESET);	247	PROCESS_EXCEPTION(EXC_RESET);
195	}	248	}
196		249
197		250
198	/** Low-level Software Interrupt Exception handler. */	251	/** Low-level Software Interrupt Exception handler. */
199	static void swi_exception_entry()	252	static void swi_exception_entry()
200	{	253	{
201	PROCESS_EXCEPTION(EXC_SWI);	254	PROCESS_EXCEPTION(EXC_SWI);
202	}	255	}
203		256
204		257
205	/** Low-level Undefined Instruction Exception handler. */	258	/** Low-level Undefined Instruction Exception handler. */
206	static void undef_instr_exception_entry()	259	static void undef_instr_exception_entry()
207	{	260	{
208	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);	261	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
209	}	262	}
210		263
211		264
212	/** Low-level Fast Interrupt Exception handler. */	265	/** Low-level Fast Interrupt Exception handler. */
213	static void fiq_exception_entry()	266	static void fiq_exception_entry()
214	{	267	{
215	PROCESS_EXCEPTION(EXC_FIQ);	268	PROCESS_EXCEPTION(EXC_FIQ);
216	}	269	}
217		270
218		271
219	/** Low-level Prefetch Abort Exception handler. */	272	/** Low-level Prefetch Abort Exception handler. */
220	static void prefetch_abort_exception_entry()	273	static void prefetch_abort_exception_entry()
221	{	274	{
222	asm("sub lr, lr, #4");	275	asm("sub lr, lr, #4");
223	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);	276	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
224	}	277	}
225		278
226		279
227	/** Low-level Data Abort Exception handler. */	280	/** Low-level Data Abort Exception handler. */
228	static void data_abort_exception_entry()	281	static void data_abort_exception_entry()
229	{	282	{
230	asm("sub lr, lr, #8");	283	asm("sub lr, lr, #8");
231	PROCESS_EXCEPTION(EXC_DATA_ABORT);	284	PROCESS_EXCEPTION(EXC_DATA_ABORT);
232	}	285	}
233		286
234		287
235	/** Low-level Interrupt Exception handler.	288	/** Low-level Interrupt Exception handler.
236	*	289	*
237	* CPU is switched to Undefined mode before further interrupt processing	290	* CPU is switched to Undefined mode before further interrupt processing
238	* because of possible occurence of nested interrupt exception, which	291	* because of possible occurence of nested interrupt exception, which
239	* would overwrite (and thus spoil) stack pointer.	292	* would overwrite (and thus spoil) stack pointer.
240	*/	293	*/
241	static void irq_exception_entry()	294	static void irq_exception_entry()
242	{	295	{
243	asm("sub lr, lr, #4");	296	asm("sub lr, lr, #4");
244	setup_stack_and_save_regs();	297	setup_stack_and_save_regs();
245		298
246	/* switch to Undefined mode */	299	switchToIrqServicingMode();
247	asm("stmfd sp!, {r0-r3}");	-
248	asm("mov r1, sp");	-
249	asm("mov r2, lr");	-
250	asm("mrs r0, cpsr");	-
251	asm("bic r0, r0, #0x1f");	-
252	asm("orr r0, r0, #0x1b");	-
253	asm("msr cpsr_c, r0");	-
254	asm("mov sp, r1");	-
255	asm("mov lr, r2");	-
256	asm("ldmfd sp!, {r0-r3}");	-
257		300
258	CALL_EXC_DISPATCH(EXC_IRQ)	301	CALL_EXC_DISPATCH(EXC_IRQ)
259		302
260	load_regs();	303	load_regs();
261	}	304	}
262		305
263		306
264	/** Software Interrupt handler.	307	/** Software Interrupt handler.
265	*	308	*
266	* Dispatches the syscall.	309	* Dispatches the syscall.
267	*/	310	*/
268	static void swi_exception(int exc_no, istate_t *istate)	311	static void swi_exception(int exc_no, istate_t *istate)
269	{	312	{
270	/*	313	/*
271	dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,	314	dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,
272	istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);	315	istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);
273	*/	316	*/
274		317
275	istate->r0 = syscall_handler(	318	istate->r0 = syscall_handler(
276	istate->r0,	319	istate->r0,
277	istate->r1,	320	istate->r1,
278	istate->r2,	321	istate->r2,
279	istate->r3,	322	istate->r3,
280	istate->r4);	323	istate->r4);
281	}	324	}
282		325
283		326
284	/** Interrupt Exception handler.	327	/** Interrupt Exception handler.
285	*	328	*
286	* Determines the sources of interrupt, and calls their handlers.	329	* Determines the sources of interrupt, and calls their handlers.
287	*/	330	*/
288	static void irq_exception(int exc_no, istate_t *istate)	331	static void irq_exception(int exc_no, istate_t *istate)
289	{	332	{
290	machine_irq_exception(exc_no, istate);	333	machine_irq_exception(exc_no, istate);
291	}	334	}
292		335
293		336
294	/** Fills exception vectors with appropriate exception handlers. */	337	/** Fills exception vectors with appropriate exception handlers. */
295	void install_exception_handlers(void)	338	void install_exception_handlers(void)
296	{	339	{
297	install_handler((unsigned)reset_exception_entry,	340	install_handler((unsigned)reset_exception_entry,
298	(unsigned*)EXC_RESET_VEC);	341	(unsigned*)EXC_RESET_VEC);
299		342
300	install_handler((unsigned)undef_instr_exception_entry,	343	install_handler((unsigned)undef_instr_exception_entry,
301	(unsigned*)EXC_UNDEF_INSTR_VEC);	344	(unsigned*)EXC_UNDEF_INSTR_VEC);
302		345
303	install_handler((unsigned)swi_exception_entry,	346	install_handler((unsigned)swi_exception_entry,
304	(unsigned*)EXC_SWI_VEC);	347	(unsigned*)EXC_SWI_VEC);
305		348
306	install_handler((unsigned)prefetch_abort_exception_entry,	349	install_handler((unsigned)prefetch_abort_exception_entry,
307	(unsigned*)EXC_PREFETCH_ABORT_VEC);	350	(unsigned*)EXC_PREFETCH_ABORT_VEC);
308		351
309	install_handler((unsigned)data_abort_exception_entry,	352	install_handler((unsigned)data_abort_exception_entry,
310	(unsigned*)EXC_DATA_ABORT_VEC);	353	(unsigned*)EXC_DATA_ABORT_VEC);
311		354
312	install_handler((unsigned)irq_exception_entry,	355	install_handler((unsigned)irq_exception_entry,
313	(unsigned*)EXC_IRQ_VEC);	356	(unsigned*)EXC_IRQ_VEC);
314		357
315	install_handler((unsigned)fiq_exception_entry,	358	install_handler((unsigned)fiq_exception_entry,
316	(unsigned*)EXC_FIQ_VEC);	359	(unsigned*)EXC_FIQ_VEC);
317	}	360	}
318		361
319		362
320	#ifdef HIGH_EXCEPTION_VECTORS	363	#ifdef HIGH_EXCEPTION_VECTORS
321	/** Activates use of high exception vectors addresses. */	364	/** Activates use of high exception vectors addresses. */
322	static void high_vectors()	365	static void high_vectors()
323	{	366	{
324	uint32_t control_reg;	367	uint32_t control_reg;
325		368
326	asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));	369	asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
327		370
328	//switch on the high vectors bit	371	//switch on the high vectors bit
329	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;	372	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;
330		373
331	asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));	374	asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
332	}	375	}
333	#endif	376	#endif
334		377
335		378
336	/** Initializes exception handling.	379	/** Initializes exception handling.
337	*	380	*
338	* Installs low-level exception handlers and then registers	381	* Installs low-level exception handlers and then registers
339	* exceptions and their handlers to kernel exception dispatcher.	382	* exceptions and their handlers to kernel exception dispatcher.
340	*/	383	*/
341	void exception_init(void)	384	void exception_init(void)
342	{	385	{
343	#ifdef HIGH_EXCEPTION_VECTORS	386	#ifdef HIGH_EXCEPTION_VECTORS
344	high_vectors();	387	high_vectors();
345	#endif	388	#endif
346	install_exception_handlers();	389	install_exception_handlers();
347		390
348	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);	391	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
349	exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);	392	exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
350	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);	393	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
351	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);	394	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
352	}	395	}
353		396
354		397
355	/** Prints #istate_t structure content.	398	/** Prints #istate_t structure content.
356	*	399	*
357	* @param istate Structure to be printed.	400	* @param istate Structure to be printed.
358	*/	401	*/
359	void print_istate(istate_t *istate)	402	void print_istate(istate_t *istate)
360	{	403	{
361	dprintf("istate dump:\n");	404	dprintf("istate dump:\n");
362		405
363	dprintf(" r0: %x r1: %x r2: %x r3: %x\n",	406	dprintf(" r0: %x r1: %x r2: %x r3: %x\n",
364	istate->r0, istate->r1, istate->r2, istate->r3);	407	istate->r0, istate->r1, istate->r2, istate->r3);
365	dprintf(" r4: %x r5: %x r6: %x r7: %x\n",	408	dprintf(" r4: %x r5: %x r6: %x r7: %x\n",
366	istate->r4, istate->r5, istate->r6, istate->r7);	409	istate->r4, istate->r5, istate->r6, istate->r7);
367	dprintf(" r8: %x r8: %x r10: %x r11: %x\n",	410	dprintf(" r8: %x r8: %x r10: %x r11: %x\n",
368	istate->r8, istate->r9, istate->r10, istate->r11);	411	istate->r8, istate->r9, istate->r10, istate->r11);
369	dprintf(" r12: %x sp: %x lr: %x spsr: %x\n",	412	dprintf(" r12: %x sp: %x lr: %x spsr: %x\n",
370	istate->r12, istate->sp, istate->lr, istate->spsr);	413	istate->r12, istate->sp, istate->lr, istate->spsr);
371		414
372	dprintf(" pc: %x\n", istate->pc);	415	dprintf(" pc: %x\n", istate->pc);
373	}	416	}
374		417
375		418
376	/** @}	419	/** @}
377	*/	420	*/
378		421

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(root)/branches/arm/kernel/arch/arm32/src/exception.c – Rev 2355 → 2407