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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * @brief Exception handlers and exception initialization routines. |
33 | * @brief Exception handlers and exception initialization routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <arch/exception.h> |
36 | #include <arch/exception.h> |
37 | #include <arch/memstr.h> |
37 | #include <arch/memstr.h> |
38 | #include <arch/regutils.h> |
38 | #include <arch/regutils.h> |
39 | #include <interrupt.h> |
39 | #include <interrupt.h> |
40 | #include <arch/mm/page_fault.h> |
40 | #include <arch/mm/page_fault.h> |
41 | #include <arch/barrier.h> |
41 | #include <arch/barrier.h> |
42 | #include <arch/machine.h> |
42 | #include <arch/machine.h> |
43 | #include <print.h> |
43 | #include <print.h> |
44 | #include <syscall/syscall.h> |
44 | #include <syscall/syscall.h> |
45 | 45 | ||
46 | /** Offset used in calculation of exception handler's relative address. |
46 | /** Offset used in calculation of exception handler's relative address. |
47 | * |
47 | * |
48 | * @see install_handler() |
48 | * @see install_handler() |
49 | */ |
49 | */ |
50 | #define PREFETCH_OFFSET 0x8 |
50 | #define PREFETCH_OFFSET 0x8 |
51 | 51 | ||
52 | /** LDR instruction's code */ |
52 | /** LDR instruction's code */ |
53 | #define LDR_OPCODE 0xe59ff000 |
53 | #define LDR_OPCODE 0xe59ff000 |
54 | 54 | ||
55 | /** Number of exception vectors. */ |
55 | /** Number of exception vectors. */ |
56 | #define EXC_VECTORS 8 |
56 | #define EXC_VECTORS 8 |
57 | 57 | ||
58 | /** Size of memory block occupied by exception vectors. */ |
58 | /** Size of memory block occupied by exception vectors. */ |
59 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
59 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
60 | 60 | ||
61 | /** Switches to kernel stack and saves all registers there. |
61 | /** Switches to kernel stack and saves all registers there. |
62 | * |
62 | * |
63 | * Temporary exception stack is used to save a few registers |
63 | * Temporary exception stack is used to save a few registers |
64 | * before stack switch takes place. |
64 | * before stack switch takes place. |
65 | * |
65 | * |
- | 66 | * The stack fram created by the function looks like: |
|
- | 67 | * |
|
- | 68 | * |_________________| |
|
- | 69 | * | | |
|
- | 70 | * | SPSR | |
|
- | 71 | * | | |
|
- | 72 | * |_________________| |
|
- | 73 | * | Stack Pointer | |
|
- | 74 | * | of | |
|
- | 75 | * | Previous Mode | |
|
- | 76 | * |_________________| |
|
- | 77 | * | Return address | |
|
- | 78 | * | of | |
|
- | 79 | * | Previous Mode | |
|
- | 80 | * |_________________| |
|
- | 81 | * | R0 - R12 | |
|
- | 82 | * | of | |
|
- | 83 | * | Previous Mode | |
|
- | 84 | * |_________________| |
|
- | 85 | * | Return address | |
|
- | 86 | * | from | |
|
- | 87 | * |Exception Handler| |
|
- | 88 | * |_________________| |
|
- | 89 | * | | |
|
- | 90 | * |
|
66 | */ |
91 | */ |
67 | inline static void setup_stack_and_save_regs() |
92 | inline static void setup_stack_and_save_regs() |
68 | { |
93 | { |
69 | asm volatile ( |
94 | asm volatile ( |
70 | "ldr r13, =exc_stack\n" |
95 | "ldr r13, =exc_stack\n" |
71 | "stmfd r13!, {r0}\n" |
96 | "stmfd r13!, {r0-r3}\n" |
- | 97 | "mrs r1, cpsr\n" |
|
- | 98 | "bic r1, r1, #0x1f\n" |
|
72 | "mrs r0, spsr\n" |
99 | "mrs r2, spsr\n" |
73 | "and r0, r0, #0x1f\n" |
100 | "and r0, r2, #0x1f\n" |
74 | "cmp r0, #0x10\n" |
101 | "cmp r0, #0x10\n" |
75 | "bne 1f\n" |
102 | "bne 1f\n" |
76 | 103 | ||
77 | /* prev mode was usermode */ |
104 | /* prev mode was usermode */ |
- | 105 | "mov r0, sp\n" |
|
78 | "ldmfd r13!, {r0}\n" |
106 | "mov r3, lr\n" |
- | 107 | ||
- | 108 | /* Switch to supervisor mode */ |
|
- | 109 | "orr r1, r1, #0x13\n" |
|
- | 110 | "msr cpsr_c, r1\n" |
|
- | 111 | ||
- | 112 | /* Load sp with [supervisor_sp] */ |
|
79 | "ldr r13, =supervisor_sp\n" |
113 | "ldr r13, =supervisor_sp\n" |
80 | "ldr r13, [r13]\n" |
114 | "ldr r13, [r13]\n" |
- | 115 | ||
- | 116 | /* Populate the stack frame */ |
|
- | 117 | "msr spsr, r2\n" |
|
- | 118 | "mov lr, r3\n" |
|
81 | "stmfd r13!, {lr}\n" |
119 | "stmfd r13!, {lr}\n" |
82 | "stmfd r13!, {r0-r12}\n" |
120 | "stmfd r13!, {r4-r12}\n" |
- | 121 | "ldmfd r0!, {r4-r7}\n" |
|
- | 122 | "stmfd r13!, {r4-r7}\n" |
|
83 | "stmfd r13!, {r13, lr}^\n" |
123 | "stmfd r13!, {r13, lr}^\n" |
84 | "mrs r0, spsr\n" |
- | |
85 | "stmfd r13!, {r0}\n" |
124 | "stmfd r13!, {r2}\n" |
86 | "b 2f\n" |
125 | "b 2f\n" |
87 | 126 | ||
- | 127 | ||
88 | /* mode was not usermode */ |
128 | /* mode was not usermode */ |
89 | "1:\n" |
129 | "1:\n" |
90 | "stmfd r13!, {r1, r2, r3}\n" |
130 | /* Switch to previous mode which is undoubtedly the supervisor mode */ |
91 | "mrs r1, cpsr\n" |
- | |
92 | "mov r2, lr\n" |
- | |
93 | "bic r1, r1, #0x1f\n" |
- | |
94 | "orr r1, r1, r0\n" |
131 | "orr r1, r1, r0\n" |
95 | "mrs r0, cpsr\n" |
132 | "mov r0, lr\n" |
- | 133 | "mov r3, sp\n" |
|
96 | "msr cpsr_c, r1\n" |
134 | "msr cpsr_c, r1\n" |
97 | 135 | ||
- | 136 | /* Populate the stack frame */ |
|
98 | "mov r3, r13\n" |
137 | "mov r1, sp\n" |
99 | "stmfd r13!, {r2}\n" |
138 | "stmfd r13!, {r0}\n" |
100 | "mov r2, lr\n" |
- | |
101 | "stmfd r13!, {r4-r12}\n" |
139 | "stmfd r13!, {r4-r12}\n" |
102 | "mov r1, r13\n" |
- | |
103 | 140 | ||
104 | /* the following two lines are for debugging */ |
141 | /* Store r0-r3 in r4-r7 and then push it on to stack */ |
105 | "mov sp, #0\n" |
142 | "ldmfd r3!, {r4-r7}\n" |
106 | "mov lr, #0\n" |
- | |
107 | "msr cpsr_c, r0\n" |
143 | "stmfd r13!, {r4-r7}\n" |
108 | 144 | ||
109 | "ldmfd r13!, {r4, r5, r6, r7}\n" |
145 | /* Push return address and stack pointer on to stack */ |
110 | "stmfd r1!, {r4, r5, r6}\n" |
- | |
111 | "stmfd r1!, {r7}\n" |
146 | "stmfd r13!, {lr}\n" |
112 | "stmfd r1!, {r2}\n" |
147 | "stmfd r13!, {r1}\n" |
113 | "stmfd r1!, {r3}\n" |
148 | "mov lr, r0\n" |
114 | "mrs r0, spsr\n" |
149 | "msr spsr, r2\n" |
115 | "stmfd r1!, {r0}\n" |
150 | "stmfd r13!, {r2}\n" |
116 | "mov r13, r1\n" |
- | |
117 | 151 | ||
118 | "2:\n" |
152 | "2:\n" |
119 | ); |
153 | ); |
120 | } |
154 | } |
121 | 155 | ||
122 | /** Returns from exception mode. |
156 | /** Returns from exception mode. |
123 | * |
157 | * |
124 | * Previously saved state of registers (including control register) |
158 | * Previously saved state of registers (including control register) |
125 | * is restored from the stack. |
159 | * is restored from the stack. |
126 | */ |
160 | */ |
127 | inline static void load_regs() |
161 | inline static void load_regs() |
128 | { |
162 | { |
129 | asm volatile( |
163 | asm volatile( |
130 | "ldmfd r13!, {r0} \n" |
164 | "ldmfd r13!, {r0} \n" |
131 | "msr spsr, r0 \n" |
165 | "msr spsr, r0 \n" |
132 | "and r0, r0, #0x1f \n" |
166 | "and r0, r0, #0x1f \n" |
133 | "cmp r0, #0x10 \n" |
167 | "cmp r0, #0x10 \n" |
134 | "bne 1f \n" |
168 | "bne 1f \n" |
135 | 169 | ||
136 | /* return to user mode */ |
170 | /* return to user mode */ |
137 | "ldmfd r13!, {r13, lr}^ \n" |
171 | "ldmfd r13!, {r13, lr}^ \n" |
138 | "b 2f \n" |
172 | "b 2f \n" |
139 | 173 | ||
140 | /* return to non-user mode */ |
174 | /* return to non-user mode */ |
141 | "1:\n" |
175 | "1:\n" |
142 | "ldmfd r13!, {r1, r2} \n" |
176 | "ldmfd r13!, {r1, r2} \n" |
143 | "mrs r3, cpsr \n" |
177 | "mrs r3, cpsr \n" |
144 | "bic r3, r3, #0x1f \n" |
178 | "bic r3, r3, #0x1f \n" |
145 | "orr r3, r3, r0 \n" |
179 | "orr r3, r3, r0 \n" |
146 | "mrs r0, cpsr \n" |
180 | "mrs r0, cpsr \n" |
147 | "msr cpsr_c, r3 \n" |
181 | "msr cpsr_c, r3 \n" |
148 | 182 | ||
149 | "mov r13, r1 \n" |
- | |
150 | "mov lr, r2 \n" |
183 | "mov lr, r2 \n" |
151 | "msr cpsr_c, r0 \n" |
184 | "msr cpsr_c, r0 \n" |
152 | 185 | ||
153 | /* actual return */ |
186 | /* actual return */ |
154 | "2:\n" |
187 | "2:\n" |
155 | "ldmfd r13!, {r0-r12, pc}^\n" |
188 | "ldmfd r13!, {r0-r12, pc}^\n" |
156 | ); |
189 | ); |
157 | } |
190 | } |
158 | 191 | ||
159 | 192 | ||
160 | /** Switch CPU to mode in which interrupts are serviced (currently it |
- | |
161 | * is Undefined mode). |
- | |
162 | * |
- | |
163 | * The default mode for interrupt servicing (Interrupt Mode) |
- | |
164 | * can not be used because of nested interrupts (which can occur |
- | |
165 | * because interrupts are enabled in higher levels of interrupt handler). |
- | |
166 | */ |
- | |
167 | inline static void switch_to_irq_servicing_mode() |
- | |
168 | { |
- | |
169 | /* switch to Undefined mode */ |
- | |
170 | asm volatile( |
- | |
171 | /* save regs used during switching */ |
- | |
172 | "stmfd sp!, {r0-r3} \n" |
- | |
173 | - | ||
174 | /* save stack pointer and link register to r1, r2 */ |
- | |
175 | "mov r1, sp \n" |
- | |
176 | "mov r2, lr \n" |
- | |
177 | - | ||
178 | /* mode switch */ |
- | |
179 | "mrs r0, cpsr \n" |
- | |
180 | "bic r0, r0, #0x1f \n" |
- | |
181 | "orr r0, r0, #0x1b \n" |
- | |
182 | "msr cpsr_c, r0 \n" |
- | |
183 | - | ||
184 | /* restore saved sp and lr */ |
- | |
185 | "mov sp, r1 \n" |
- | |
186 | "mov lr, r2 \n" |
- | |
187 | - | ||
188 | /* restore original regs */ |
- | |
189 | "ldmfd sp!, {r0-r3} \n" |
- | |
190 | ); |
- | |
191 | } |
- | |
192 | - | ||
193 | /** Calls exception dispatch routine. */ |
193 | /** Calls exception dispatch routine. */ |
194 | #define CALL_EXC_DISPATCH(exception) \ |
194 | #define CALL_EXC_DISPATCH(exception) \ |
195 | asm volatile ( \ |
195 | asm volatile ( \ |
196 | "mov r0, %[exc]\n" \ |
196 | "mov r0, %[exc]\n" \ |
197 | "mov r1, r13\n" \ |
197 | "mov r1, r13\n" \ |
198 | "bl exc_dispatch\n" \ |
198 | "bl exc_dispatch\n" \ |
199 | :: [exc] "i" (exception) \ |
199 | :: [exc] "i" (exception) \ |
200 | );\ |
200 | );\ |
201 | 201 | ||
202 | /** General exception handler. |
202 | /** General exception handler. |
203 | * |
203 | * |
204 | * Stores registers, dispatches the exception, |
204 | * Stores registers, dispatches the exception, |
205 | * and finally restores registers and returns from exception processing. |
205 | * and finally restores registers and returns from exception processing. |
206 | * |
206 | * |
207 | * @param exception Exception number. |
207 | * @param exception Exception number. |
208 | */ |
208 | */ |
209 | #define PROCESS_EXCEPTION(exception) \ |
209 | #define PROCESS_EXCEPTION(exception) \ |
210 | setup_stack_and_save_regs(); \ |
210 | setup_stack_and_save_regs(); \ |
211 | CALL_EXC_DISPATCH(exception) \ |
211 | CALL_EXC_DISPATCH(exception) \ |
212 | load_regs(); |
212 | load_regs(); |
213 | 213 | ||
214 | /** Updates specified exception vector to jump to given handler. |
214 | /** Updates specified exception vector to jump to given handler. |
215 | * |
215 | * |
216 | * Addresses of handlers are stored in memory following exception vectors. |
216 | * Addresses of handlers are stored in memory following exception vectors. |
217 | */ |
217 | */ |
218 | static void install_handler(unsigned handler_addr, unsigned *vector) |
218 | static void install_handler(unsigned handler_addr, unsigned *vector) |
219 | { |
219 | { |
220 | /* relative address (related to exc. vector) of the word |
220 | /* relative address (related to exc. vector) of the word |
221 | * where handler's address is stored |
221 | * where handler's address is stored |
222 | */ |
222 | */ |
223 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - |
223 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - |
224 | PREFETCH_OFFSET; |
224 | PREFETCH_OFFSET; |
225 | 225 | ||
226 | /* make it LDR instruction and store at exception vector */ |
226 | /* make it LDR instruction and store at exception vector */ |
227 | *vector = handler_address_ptr | LDR_OPCODE; |
227 | *vector = handler_address_ptr | LDR_OPCODE; |
228 | smc_coherence(*vector); |
228 | smc_coherence(*vector); |
229 | 229 | ||
230 | /* store handler's address */ |
230 | /* store handler's address */ |
231 | *(vector + EXC_VECTORS) = handler_addr; |
231 | *(vector + EXC_VECTORS) = handler_addr; |
232 | 232 | ||
233 | } |
233 | } |
234 | 234 | ||
235 | /** Low-level Reset Exception handler. */ |
235 | /** Low-level Reset Exception handler. */ |
236 | static void reset_exception_entry(void) |
236 | static void reset_exception_entry(void) |
237 | { |
237 | { |
238 | PROCESS_EXCEPTION(EXC_RESET); |
238 | PROCESS_EXCEPTION(EXC_RESET); |
239 | } |
239 | } |
240 | 240 | ||
241 | /** Low-level Software Interrupt Exception handler. */ |
241 | /** Low-level Software Interrupt Exception handler. */ |
242 | static void swi_exception_entry(void) |
242 | static void swi_exception_entry(void) |
243 | { |
243 | { |
244 | PROCESS_EXCEPTION(EXC_SWI); |
244 | PROCESS_EXCEPTION(EXC_SWI); |
245 | } |
245 | } |
246 | 246 | ||
247 | /** Low-level Undefined Instruction Exception handler. */ |
247 | /** Low-level Undefined Instruction Exception handler. */ |
248 | static void undef_instr_exception_entry(void) |
248 | static void undef_instr_exception_entry(void) |
249 | { |
249 | { |
250 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
250 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
251 | } |
251 | } |
252 | 252 | ||
253 | /** Low-level Fast Interrupt Exception handler. */ |
253 | /** Low-level Fast Interrupt Exception handler. */ |
254 | static void fiq_exception_entry(void) |
254 | static void fiq_exception_entry(void) |
255 | { |
255 | { |
256 | PROCESS_EXCEPTION(EXC_FIQ); |
256 | PROCESS_EXCEPTION(EXC_FIQ); |
257 | } |
257 | } |
258 | 258 | ||
259 | /** Low-level Prefetch Abort Exception handler. */ |
259 | /** Low-level Prefetch Abort Exception handler. */ |
260 | static void prefetch_abort_exception_entry(void) |
260 | static void prefetch_abort_exception_entry(void) |
261 | { |
261 | { |
262 | asm volatile ( |
262 | asm volatile ( |
263 | "sub lr, lr, #4" |
263 | "sub lr, lr, #4" |
264 | ); |
264 | ); |
265 | 265 | ||
266 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
266 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
267 | } |
267 | } |
268 | 268 | ||
269 | /** Low-level Data Abort Exception handler. */ |
269 | /** Low-level Data Abort Exception handler. */ |
270 | static void data_abort_exception_entry(void) |
270 | static void data_abort_exception_entry(void) |
271 | { |
271 | { |
272 | asm volatile ( |
272 | asm volatile ( |
273 | "sub lr, lr, #8" |
273 | "sub lr, lr, #8" |
274 | ); |
274 | ); |
275 | 275 | ||
276 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
276 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
277 | } |
277 | } |
278 | 278 | ||
279 | /** Low-level Interrupt Exception handler. |
279 | /** Low-level Interrupt Exception handler. |
280 | * |
280 | * |
281 | * CPU is switched to Undefined mode before further interrupt processing |
281 | * CPU is switched to Undefined mode before further interrupt processing |
282 | * because of possible occurence of nested interrupt exception, which |
282 | * because of possible occurence of nested interrupt exception, which |
283 | * would overwrite (and thus spoil) stack pointer. |
283 | * would overwrite (and thus spoil) stack pointer. |
284 | */ |
284 | */ |
285 | static void irq_exception_entry(void) |
285 | static void irq_exception_entry(void) |
286 | { |
286 | { |
287 | asm volatile ( |
287 | asm volatile ( |
288 | "sub lr, lr, #4" |
288 | "sub lr, lr, #4" |
289 | ); |
289 | ); |
290 | 290 | ||
291 | setup_stack_and_save_regs(); |
- | |
292 | - | ||
293 | switch_to_irq_servicing_mode(); |
- | |
294 | - | ||
295 | CALL_EXC_DISPATCH(EXC_IRQ) |
291 | PROCESS_EXCEPTION(EXC_IRQ) |
296 | - | ||
297 | load_regs(); |
- | |
298 | } |
292 | } |
299 | 293 | ||
300 | /** Software Interrupt handler. |
294 | /** Software Interrupt handler. |
301 | * |
295 | * |
302 | * Dispatches the syscall. |
296 | * Dispatches the syscall. |
303 | */ |
297 | */ |
304 | static void swi_exception(int exc_no, istate_t *istate) |
298 | static void swi_exception(int exc_no, istate_t *istate) |
305 | { |
299 | { |
306 | istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2, |
300 | istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2, |
307 | istate->r3, istate->r4, istate->r5, istate->r6); |
301 | istate->r3, istate->r4, istate->r5, istate->r6); |
308 | } |
302 | } |
309 | 303 | ||
310 | /** Fills exception vectors with appropriate exception handlers. */ |
304 | /** Fills exception vectors with appropriate exception handlers. */ |
311 | void install_exception_handlers(void) |
305 | void install_exception_handlers(void) |
312 | { |
306 | { |
313 | install_handler((unsigned) reset_exception_entry, |
307 | install_handler((unsigned) reset_exception_entry, |
314 | (unsigned *) EXC_RESET_VEC); |
308 | (unsigned *) EXC_RESET_VEC); |
315 | 309 | ||
316 | install_handler((unsigned) undef_instr_exception_entry, |
310 | install_handler((unsigned) undef_instr_exception_entry, |
317 | (unsigned *) EXC_UNDEF_INSTR_VEC); |
311 | (unsigned *) EXC_UNDEF_INSTR_VEC); |
318 | 312 | ||
319 | install_handler((unsigned) swi_exception_entry, |
313 | install_handler((unsigned) swi_exception_entry, |
320 | (unsigned *) EXC_SWI_VEC); |
314 | (unsigned *) EXC_SWI_VEC); |
321 | 315 | ||
322 | install_handler((unsigned) prefetch_abort_exception_entry, |
316 | install_handler((unsigned) prefetch_abort_exception_entry, |
323 | (unsigned *) EXC_PREFETCH_ABORT_VEC); |
317 | (unsigned *) EXC_PREFETCH_ABORT_VEC); |
324 | 318 | ||
325 | install_handler((unsigned) data_abort_exception_entry, |
319 | install_handler((unsigned) data_abort_exception_entry, |
326 | (unsigned *) EXC_DATA_ABORT_VEC); |
320 | (unsigned *) EXC_DATA_ABORT_VEC); |
327 | 321 | ||
328 | install_handler((unsigned) irq_exception_entry, |
322 | install_handler((unsigned) irq_exception_entry, |
329 | (unsigned *) EXC_IRQ_VEC); |
323 | (unsigned *) EXC_IRQ_VEC); |
330 | 324 | ||
331 | install_handler((unsigned) fiq_exception_entry, |
325 | install_handler((unsigned) fiq_exception_entry, |
332 | (unsigned *) EXC_FIQ_VEC); |
326 | (unsigned *) EXC_FIQ_VEC); |
333 | } |
327 | } |
334 | 328 | ||
335 | #ifdef HIGH_EXCEPTION_VECTORS |
329 | #ifdef HIGH_EXCEPTION_VECTORS |
336 | /** Activates use of high exception vectors addresses. */ |
330 | /** Activates use of high exception vectors addresses. */ |
337 | static void high_vectors(void) |
331 | static void high_vectors(void) |
338 | { |
332 | { |
339 | uint32_t control_reg; |
333 | uint32_t control_reg; |
340 | 334 | ||
341 | asm volatile ( |
335 | asm volatile ( |
342 | "mrc p15, 0, %[control_reg], c1, c1" |
336 | "mrc p15, 0, %[control_reg], c1, c1" |
343 | : [control_reg] "=r" (control_reg) |
337 | : [control_reg] "=r" (control_reg) |
344 | ); |
338 | ); |
345 | 339 | ||
346 | /* switch on the high vectors bit */ |
340 | /* switch on the high vectors bit */ |
347 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
341 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
348 | 342 | ||
349 | asm volatile ( |
343 | asm volatile ( |
350 | "mcr p15, 0, %[control_reg], c1, c1" |
344 | "mcr p15, 0, %[control_reg], c1, c1" |
351 | :: [control_reg] "r" (control_reg) |
345 | :: [control_reg] "r" (control_reg) |
352 | ); |
346 | ); |
353 | } |
347 | } |
354 | #endif |
348 | #endif |
355 | 349 | ||
356 | /** Interrupt Exception handler. |
350 | /** Interrupt Exception handler. |
357 | * |
351 | * |
358 | * Determines the sources of interrupt and calls their handlers. |
352 | * Determines the sources of interrupt and calls their handlers. |
359 | */ |
353 | */ |
360 | static void irq_exception(int exc_no, istate_t *istate) |
354 | static void irq_exception(int exc_no, istate_t *istate) |
361 | { |
355 | { |
362 | machine_irq_exception(exc_no, istate); |
356 | machine_irq_exception(exc_no, istate); |
363 | } |
357 | } |
364 | 358 | ||
365 | /** Initializes exception handling. |
359 | /** Initializes exception handling. |
366 | * |
360 | * |
367 | * Installs low-level exception handlers and then registers |
361 | * Installs low-level exception handlers and then registers |
368 | * exceptions and their handlers to kernel exception dispatcher. |
362 | * exceptions and their handlers to kernel exception dispatcher. |
369 | */ |
363 | */ |
370 | void exception_init(void) |
364 | void exception_init(void) |
371 | { |
365 | { |
372 | #ifdef HIGH_EXCEPTION_VECTORS |
366 | #ifdef HIGH_EXCEPTION_VECTORS |
373 | high_vectors(); |
367 | high_vectors(); |
374 | #endif |
368 | #endif |
375 | install_exception_handlers(); |
369 | install_exception_handlers(); |
376 | 370 | ||
377 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
371 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
378 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", |
372 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", |
379 | (iroutine) prefetch_abort); |
373 | (iroutine) prefetch_abort); |
380 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
374 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
381 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
375 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
382 | } |
376 | } |
383 | 377 | ||
384 | /** Prints #istate_t structure content. |
378 | /** Prints #istate_t structure content. |
385 | * |
379 | * |
386 | * @param istate Structure to be printed. |
380 | * @param istate Structure to be printed. |
387 | */ |
381 | */ |
388 | void print_istate(istate_t *istate) |
382 | void print_istate(istate_t *istate) |
389 | { |
383 | { |
390 | printf("istate dump:\n"); |
384 | printf("istate dump:\n"); |
391 | 385 | ||
392 | printf(" r0: %x r1: %x r2: %x r3: %x\n", |
386 | printf(" r0: %x r1: %x r2: %x r3: %x\n", |
393 | istate->r0, istate->r1, istate->r2, istate->r3); |
387 | istate->r0, istate->r1, istate->r2, istate->r3); |
394 | printf(" r4: %x r5: %x r6: %x r7: %x\n", |
388 | printf(" r4: %x r5: %x r6: %x r7: %x\n", |
395 | istate->r4, istate->r5, istate->r6, istate->r7); |
389 | istate->r4, istate->r5, istate->r6, istate->r7); |
396 | printf(" r8: %x r8: %x r10: %x r11: %x\n", |
390 | printf(" r8: %x r8: %x r10: %x r11: %x\n", |
397 | istate->r8, istate->r9, istate->r10, istate->r11); |
391 | istate->r8, istate->r9, istate->r10, istate->r11); |
398 | printf(" r12: %x sp: %x lr: %x spsr: %x\n", |
392 | printf(" r12: %x sp: %x lr: %x spsr: %x\n", |
399 | istate->r12, istate->sp, istate->lr, istate->spsr); |
393 | istate->r12, istate->sp, istate->lr, istate->spsr); |
400 | 394 | ||
401 | printf(" pc: %x\n", istate->pc); |
395 | printf(" pc: %x\n", istate->pc); |
402 | } |
396 | } |
403 | 397 | ||
404 | /** @} |
398 | /** @} |
405 | */ |
399 | */ |
406 | 400 |