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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * @brief Exception handlers and exception initialization routines. |
33 | * @brief Exception handlers and exception initialization routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | - | ||
37 | #include <arch/exception.h> |
36 | #include <arch/exception.h> |
38 | #include <arch/debug/print.h> |
37 | #include <arch/debug/print.h> |
39 | #include <arch/memstr.h> |
38 | #include <arch/memstr.h> |
40 | #include <arch/regutils.h> |
39 | #include <arch/regutils.h> |
41 | #include <interrupt.h> |
40 | #include <interrupt.h> |
42 | #include <arch/machine.h> |
41 | #include <arch/machine.h> |
43 | #include <arch/mm/page_fault.h> |
42 | #include <arch/mm/page_fault.h> |
44 | #include <print.h> |
43 | #include <print.h> |
45 | #include <syscall/syscall.h> |
44 | #include <syscall/syscall.h> |
46 | 45 | ||
47 | /** Offset used in calculation of exception handler's relative address. |
46 | /** Offset used in calculation of exception handler's relative address. |
48 | * |
47 | * |
49 | * @see install_handler() |
48 | * @see install_handler() |
50 | */ |
49 | */ |
51 | #define PREFETCH_OFFSET 0x8 |
50 | #define PREFETCH_OFFSET 0x8 |
52 | 51 | ||
53 | /** LDR instruction's code */ |
52 | /** LDR instruction's code */ |
54 | #define LDR_OPCODE 0xe59ff000 |
53 | #define LDR_OPCODE 0xe59ff000 |
55 | 54 | ||
56 | /** Number of exception vectors. */ |
55 | /** Number of exception vectors. */ |
57 | #define EXC_VECTORS 8 |
56 | #define EXC_VECTORS 8 |
58 | 57 | ||
59 | /** Size of memory block occupied by exception vectors. */ |
58 | /** Size of memory block occupied by exception vectors. */ |
60 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
59 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
61 | 60 | ||
62 | - | ||
63 | /** Switches to kernel stack and saves all registers there. |
61 | /** Switches to kernel stack and saves all registers there. |
64 | * |
62 | * |
65 | * Temporary exception stack is used to save a few registers |
63 | * Temporary exception stack is used to save a few registers |
66 | * before stack switch takes place. |
64 | * before stack switch takes place. |
67 | */ |
65 | */ |
68 | inline static void setup_stack_and_save_regs() |
66 | inline static void setup_stack_and_save_regs() |
69 | { |
67 | { |
- | 68 | asm volatile( |
|
70 | asm volatile("ldr r13, =exc_stack \n\ |
69 | "ldr r13, =exc_stack \n" |
71 | stmfd r13!, {r0} \n\ |
70 | "stmfd r13!, {r0} \n" |
72 | mrs r0, spsr \n\ |
71 | "mrs r0, spsr \n" |
73 | and r0, r0, #0x1f \n\ |
72 | "and r0, r0, #0x1f \n" |
74 | cmp r0, #0x10 \n\ |
73 | "cmp r0, #0x10 \n" |
75 | bne 1f \n\ |
74 | "bne 1f \n" |
76 | \n\ |
75 | |
77 | @prev mode was usermode \n\ |
76 | /* prev mode was usermode */ |
78 | ldmfd r13!, {r0} \n\ |
77 | "ldmfd r13!, {r0} \n" |
79 | ldr r13, =supervisor_sp \n\ |
78 | "ldr r13, =supervisor_sp \n" |
80 | ldr r13, [r13] \n\ |
79 | "ldr r13, [r13] \n" |
81 | stmfd r13!, {lr} \n\ |
80 | "stmfd r13!, {lr} \n" |
82 | stmfd r13!, {r0-r12} \n\ |
81 | "stmfd r13!, {r0-r12} \n" |
83 | stmfd r13!, {r13, lr}^ \n\ |
82 | "stmfd r13!, {r13, lr}^ \n" |
84 | mrs r0, spsr \n\ |
83 | "mrs r0, spsr \n" |
85 | stmfd r13!, {r0} \n\ |
84 | "stmfd r13!, {r0} \n" |
86 | b 2f \n\ |
85 | "b 2f \n" |
87 | \n\ |
86 | |
88 | @prev mode was not usermode \n\ |
87 | /* mode was not usermode */ |
89 | 1: \n\ |
88 | "1:\n" |
90 | stmfd r13!, {r1, r2, r3} \n\ |
89 | "stmfd r13!, {r1, r2, r3} \n" |
91 | mrs r1, cpsr \n\ |
90 | "mrs r1, cpsr \n" |
92 | mov r2, lr \n\ |
91 | "mov r2, lr \n" |
93 | bic r1, r1, #0x1f \n\ |
92 | "bic r1, r1, #0x1f \n" |
94 | orr r1, r1, r0 \n\ |
93 | "orr r1, r1, r0 \n" |
95 | mrs r0, cpsr \n\ |
94 | "mrs r0, cpsr \n" |
96 | msr cpsr_c, r1 \n\ |
95 | "msr cpsr_c, r1 \n" |
97 | \n\ |
96 | |
98 | mov r3, r13 \n\ |
97 | "mov r3, r13 \n" |
99 | stmfd r13!, {r2} \n\ |
98 | "stmfd r13!, {r2} \n" |
100 | mov r2, lr \n\ |
99 | "mov r2, lr \n" |
101 | stmfd r13!, {r4-r12} \n\ |
100 | "stmfd r13!, {r4-r12} \n" |
102 | mov r1, r13 \n\ |
101 | "mov r1, r13 \n" |
103 | @following two lines are for debugging \n\ |
102 | /* the following two lines are for debugging */ |
104 | mov sp, #0 \n\ |
103 | "mov sp, #0 \n" |
105 | mov lr, #0 \n\ |
104 | "mov lr, #0 \n" |
106 | msr cpsr_c, r0 \n\ |
105 | "msr cpsr_c, r0 \n" |
107 | \n\ |
106 | |
108 | ldmfd r13!, {r4, r5, r6, r7} \n\ |
107 | "ldmfd r13!, {r4, r5, r6, r7} \n" |
109 | stmfd r1!, {r4, r5, r6} \n\ |
108 | "stmfd r1!, {r4, r5, r6} \n" |
110 | stmfd r1!, {r7} \n\ |
109 | "stmfd r1!, {r7} \n" |
111 | stmfd r1!, {r2} \n\ |
110 | "stmfd r1!, {r2} \n" |
112 | stmfd r1!, {r3} \n\ |
111 | "stmfd r1!, {r3} \n" |
113 | mrs r0, spsr \n\ |
112 | "mrs r0, spsr \n" |
114 | stmfd r1!, {r0} \n\ |
113 | "stmfd r1!, {r0} \n" |
115 | mov r13, r1 \n\ |
114 | "mov r13, r1 \n" |
116 | 2:" |
115 | "2:\n" |
117 | ); |
116 | ); |
118 | } |
117 | } |
119 | 118 | ||
120 | - | ||
121 | /** Returns from exception mode. |
119 | /** Returns from exception mode. |
122 | * |
120 | * |
123 | * Previously saved state of registers (including control register) |
121 | * Previously saved state of registers (including control register) |
124 | * is restored from the stack. |
122 | * is restored from the stack. |
125 | */ |
123 | */ |
126 | inline static void load_regs() |
124 | inline static void load_regs() |
127 | { |
125 | { |
- | 126 | asm volatile( |
|
128 | asm volatile( "ldmfd r13!, {r0} \n\ |
127 | "ldmfd r13!, {r0} \n" |
129 | msr spsr, r0 \n\ |
128 | "msr spsr, r0 \n" |
130 | and r0, r0, #0x1f \n\ |
129 | "and r0, r0, #0x1f \n" |
131 | cmp r0, #0x10 \n\ |
130 | "cmp r0, #0x10 \n" |
132 | bne 3f \n\ |
131 | "bne 1f \n" |
133 | \n\ |
132 | |
134 | @return to user mode \n\ |
133 | /* return to user mode */ |
135 | ldmfd r13!, {r13, lr}^ \n\ |
134 | "ldmfd r13!, {r13, lr}^ \n" |
136 | b 4f \n\ |
135 | "b 2f \n" |
137 | \n\ |
136 | |
138 | @return to non-user mode \n\ |
137 | /* return to non-user mode */ |
139 | 3: \n\ |
138 | "1:\n" |
140 | ldmfd r13!, {r1, r2} \n\ |
139 | "ldmfd r13!, {r1, r2} \n" |
141 | mrs r3, cpsr \n\ |
140 | "mrs r3, cpsr \n" |
142 | bic r3, r3, #0x1f \n\ |
141 | "bic r3, r3, #0x1f \n" |
143 | orr r3, r3, r0 \n\ |
142 | "orr r3, r3, r0 \n" |
144 | mrs r0, cpsr \n\ |
143 | "mrs r0, cpsr \n" |
145 | msr cpsr_c, r3 \n\ |
144 | "msr cpsr_c, r3 \n" |
146 | \n\ |
145 | |
147 | mov r13, r1 \n\ |
146 | "mov r13, r1 \n" |
148 | mov lr, r2 \n\ |
147 | "mov lr, r2 \n" |
149 | msr cpsr_c, r0 \n\ |
148 | "msr cpsr_c, r0 \n" |
150 | \n\ |
149 | |
151 | @actual return \n\ |
150 | /* actual return */ |
- | 151 | "2:\n" |
|
152 | 4: ldmfd r13, {r0-r12, pc}^" |
152 | "ldmfd r13, {r0-r12, pc}^\n" |
153 | ); |
153 | ); |
154 | } |
154 | } |
155 | 155 | ||
156 | 156 | ||
157 | /** Switch CPU to mode in which interrupts are serviced (currently it |
157 | /** Switch CPU to mode in which interrupts are serviced (currently it |
158 | * is Undefined mode). |
158 | * is Undefined mode). |
159 | * |
159 | * |
160 | * The default mode for interrupt servicing (Interrupt Mode) |
160 | * The default mode for interrupt servicing (Interrupt Mode) |
161 | * can not be used because of nested interrupts (which can occur |
161 | * can not be used because of nested interrupts (which can occur |
162 | * because interrupt are enabled in higher levels of interrupt handler). |
162 | * because interrupts are enabled in higher levels of interrupt handler). |
163 | */ |
163 | */ |
164 | inline static void switch_to_irq_servicing_mode() |
164 | inline static void switch_to_irq_servicing_mode() |
165 | { |
165 | { |
166 | /* switch to Undefined mode */ |
166 | /* switch to Undefined mode */ |
167 | asm volatile( |
167 | asm volatile( |
168 | /* save regs used during switching */ |
168 | /* save regs used during switching */ |
169 | "stmfd sp!, {r0-r3} \n" |
169 | "stmfd sp!, {r0-r3} \n" |
170 | 170 | ||
171 | /* save stack pointer and link register to r1, r2 */ |
171 | /* save stack pointer and link register to r1, r2 */ |
172 | "mov r1, sp \n" |
172 | "mov r1, sp \n" |
173 | "mov r2, lr \n" |
173 | "mov r2, lr \n" |
174 | 174 | ||
175 | /* mode switch */ |
175 | /* mode switch */ |
176 | "mrs r0, cpsr \n" |
176 | "mrs r0, cpsr \n" |
177 | "bic r0, r0, #0x1f \n" |
177 | "bic r0, r0, #0x1f \n" |
178 | "orr r0, r0, #0x1b \n" |
178 | "orr r0, r0, #0x1b \n" |
179 | "msr cpsr_c, r0 \n" |
179 | "msr cpsr_c, r0 \n" |
180 | 180 | ||
181 | /* restore saved sp and lr */ |
181 | /* restore saved sp and lr */ |
182 | "mov sp, r1 \n" |
182 | "mov sp, r1 \n" |
183 | "mov lr, r2 \n" |
183 | "mov lr, r2 \n" |
184 | 184 | ||
185 | /* restore original regs */ |
185 | /* restore original regs */ |
186 | "ldmfd sp!, {r0-r3} \n" |
186 | "ldmfd sp!, {r0-r3} \n" |
187 | ); |
187 | ); |
188 | } |
188 | } |
189 | 189 | ||
190 | - | ||
191 | /** Calls exception dispatch routine. */ |
190 | /** Calls exception dispatch routine. */ |
192 | #define CALL_EXC_DISPATCH(exception) \ |
191 | #define CALL_EXC_DISPATCH(exception) \ |
193 | asm("mov r0, %0" : : "i" (exception)); \ |
192 | asm("mov r0, %0" : : "i" (exception)); \ |
194 | asm("mov r1, r13"); \ |
193 | asm("mov r1, r13"); \ |
195 | asm("bl exc_dispatch"); |
194 | asm("bl exc_dispatch"); |
196 | 195 | ||
197 | - | ||
198 | /** General exception handler. |
196 | /** General exception handler. |
199 | * |
197 | * |
200 | * Stores registers, dispatches the exception, |
198 | * Stores registers, dispatches the exception, |
201 | * and finally restores registers and returns from exception processing. |
199 | * and finally restores registers and returns from exception processing. |
202 | * |
200 | * |
203 | * @param exception Exception number. |
201 | * @param exception Exception number. |
204 | */ |
202 | */ |
205 | #define PROCESS_EXCEPTION(exception) \ |
203 | #define PROCESS_EXCEPTION(exception) \ |
206 | setup_stack_and_save_regs(); \ |
204 | setup_stack_and_save_regs(); \ |
207 | CALL_EXC_DISPATCH(exception) \ |
205 | CALL_EXC_DISPATCH(exception) \ |
208 | load_regs(); |
206 | load_regs(); |
209 | 207 | ||
210 | - | ||
211 | /** Updates specified exception vector to jump to given handler. |
208 | /** Updates specified exception vector to jump to given handler. |
212 | * |
209 | * |
213 | * Addresses of handlers are stored in memory following exception vectors. |
210 | * Addresses of handlers are stored in memory following exception vectors. |
214 | */ |
211 | */ |
215 | static void install_handler (unsigned handler_addr, unsigned* vector) |
212 | static void install_handler (unsigned handler_addr, unsigned* vector) |
216 | { |
213 | { |
217 | /* relative address (related to exc. vector) of the word |
214 | /* relative address (related to exc. vector) of the word |
218 | * where handler's address is stored |
215 | * where handler's address is stored |
219 | */ |
216 | */ |
220 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
217 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
221 | 218 | ||
222 | /* make it LDR instruction and store at exception vector */ |
219 | /* make it LDR instruction and store at exception vector */ |
223 | *vector = handler_address_ptr | LDR_OPCODE; |
220 | *vector = handler_address_ptr | LDR_OPCODE; |
224 | 221 | ||
225 | /* store handler's address */ |
222 | /* store handler's address */ |
226 | *(vector + EXC_VECTORS) = handler_addr; |
223 | *(vector + EXC_VECTORS) = handler_addr; |
227 | 224 | ||
228 | } |
225 | } |
229 | 226 | ||
230 | - | ||
231 | /** Low-level Reset Exception handler. */ |
227 | /** Low-level Reset Exception handler. */ |
232 | static void reset_exception_entry() |
228 | static void reset_exception_entry() |
233 | { |
229 | { |
234 | PROCESS_EXCEPTION(EXC_RESET); |
230 | PROCESS_EXCEPTION(EXC_RESET); |
235 | } |
231 | } |
236 | 232 | ||
237 | - | ||
238 | /** Low-level Software Interrupt Exception handler. */ |
233 | /** Low-level Software Interrupt Exception handler. */ |
239 | static void swi_exception_entry() |
234 | static void swi_exception_entry() |
240 | { |
235 | { |
241 | PROCESS_EXCEPTION(EXC_SWI); |
236 | PROCESS_EXCEPTION(EXC_SWI); |
242 | } |
237 | } |
243 | 238 | ||
244 | - | ||
245 | /** Low-level Undefined Instruction Exception handler. */ |
239 | /** Low-level Undefined Instruction Exception handler. */ |
246 | static void undef_instr_exception_entry() |
240 | static void undef_instr_exception_entry() |
247 | { |
241 | { |
248 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
242 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
249 | } |
243 | } |
250 | 244 | ||
251 | - | ||
252 | /** Low-level Fast Interrupt Exception handler. */ |
245 | /** Low-level Fast Interrupt Exception handler. */ |
253 | static void fiq_exception_entry() |
246 | static void fiq_exception_entry() |
254 | { |
247 | { |
255 | PROCESS_EXCEPTION(EXC_FIQ); |
248 | PROCESS_EXCEPTION(EXC_FIQ); |
256 | } |
249 | } |
257 | 250 | ||
258 | - | ||
259 | /** Low-level Prefetch Abort Exception handler. */ |
251 | /** Low-level Prefetch Abort Exception handler. */ |
260 | static void prefetch_abort_exception_entry() |
252 | static void prefetch_abort_exception_entry() |
261 | { |
253 | { |
262 | asm("sub lr, lr, #4"); |
254 | asm("sub lr, lr, #4"); |
263 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
255 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
264 | } |
256 | } |
265 | 257 | ||
266 | - | ||
267 | /** Low-level Data Abort Exception handler. */ |
258 | /** Low-level Data Abort Exception handler. */ |
268 | static void data_abort_exception_entry() |
259 | static void data_abort_exception_entry() |
269 | { |
260 | { |
270 | asm("sub lr, lr, #8"); |
261 | asm("sub lr, lr, #8"); |
271 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
262 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
272 | } |
263 | } |
273 | 264 | ||
274 | - | ||
275 | /** Low-level Interrupt Exception handler. |
265 | /** Low-level Interrupt Exception handler. |
276 | * |
266 | * |
277 | * CPU is switched to Undefined mode before further interrupt processing |
267 | * CPU is switched to Undefined mode before further interrupt processing |
278 | * because of possible occurence of nested interrupt exception, which |
268 | * because of possible occurence of nested interrupt exception, which |
279 | * would overwrite (and thus spoil) stack pointer. |
269 | * would overwrite (and thus spoil) stack pointer. |
280 | */ |
270 | */ |
281 | static void irq_exception_entry() |
271 | static void irq_exception_entry() |
282 | { |
272 | { |
283 | asm("sub lr, lr, #4"); |
273 | asm("sub lr, lr, #4"); |
284 | setup_stack_and_save_regs(); |
274 | setup_stack_and_save_regs(); |
285 | 275 | ||
286 | switch_to_irq_servicing_mode(); |
276 | switch_to_irq_servicing_mode(); |
287 | 277 | ||
288 | CALL_EXC_DISPATCH(EXC_IRQ) |
278 | CALL_EXC_DISPATCH(EXC_IRQ) |
289 | 279 | ||
290 | load_regs(); |
280 | load_regs(); |
291 | } |
281 | } |
292 | 282 | ||
293 | - | ||
294 | /** Software Interrupt handler. |
283 | /** Software Interrupt handler. |
295 | * |
284 | * |
296 | * Dispatches the syscall. |
285 | * Dispatches the syscall. |
297 | */ |
286 | */ |
298 | static void swi_exception(int exc_no, istate_t *istate) |
287 | static void swi_exception(int exc_no, istate_t *istate) |
299 | { |
288 | { |
300 | /* |
289 | /* |
301 | dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0, |
290 | dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0, |
302 | istate->r1, istate->r2, istate->r3, istate->r4, istate->pc); |
291 | istate->r1, istate->r2, istate->r3, istate->r4, istate->pc); |
303 | */ |
292 | */ |
304 | 293 | ||
305 | istate->r0 = syscall_handler( |
294 | istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2, |
306 | istate->r0, |
- | |
307 | istate->r1, |
- | |
308 | istate->r2, |
- | |
309 | istate->r3, |
- | |
310 | istate->r4); |
295 | istate->r3, istate->r4); |
311 | } |
296 | } |
312 | 297 | ||
313 | - | ||
314 | /** Interrupt Exception handler. |
298 | /** Interrupt Exception handler. |
315 | * |
299 | * |
316 | * Determines the sources of interrupt, and calls their handlers. |
300 | * Determines the sources of interrupt and calls their handlers. |
317 | */ |
301 | */ |
318 | static void irq_exception(int exc_no, istate_t *istate) |
302 | static void irq_exception(int exc_no, istate_t *istate) |
319 | { |
303 | { |
320 | machine_irq_exception(exc_no, istate); |
304 | machine_irq_exception(exc_no, istate); |
321 | } |
305 | } |
322 | 306 | ||
323 | - | ||
324 | /** Fills exception vectors with appropriate exception handlers. */ |
307 | /** Fills exception vectors with appropriate exception handlers. */ |
325 | void install_exception_handlers(void) |
308 | void install_exception_handlers(void) |
326 | { |
309 | { |
327 | install_handler((unsigned)reset_exception_entry, |
310 | install_handler((unsigned) reset_exception_entry, |
328 | (unsigned*)EXC_RESET_VEC); |
311 | (unsigned *) EXC_RESET_VEC); |
329 | 312 | ||
330 | install_handler((unsigned)undef_instr_exception_entry, |
313 | install_handler((unsigned) undef_instr_exception_entry, |
331 | (unsigned*)EXC_UNDEF_INSTR_VEC); |
314 | (unsigned *) EXC_UNDEF_INSTR_VEC); |
332 | 315 | ||
333 | install_handler((unsigned)swi_exception_entry, |
316 | install_handler((unsigned) swi_exception_entry, |
334 | (unsigned*)EXC_SWI_VEC); |
317 | (unsigned *) EXC_SWI_VEC); |
335 | 318 | ||
336 | install_handler((unsigned)prefetch_abort_exception_entry, |
319 | install_handler((unsigned) prefetch_abort_exception_entry, |
337 | (unsigned*)EXC_PREFETCH_ABORT_VEC); |
320 | (unsigned *) EXC_PREFETCH_ABORT_VEC); |
338 | 321 | ||
339 | install_handler((unsigned)data_abort_exception_entry, |
322 | install_handler((unsigned) data_abort_exception_entry, |
340 | (unsigned*)EXC_DATA_ABORT_VEC); |
323 | (unsigned *) EXC_DATA_ABORT_VEC); |
341 | 324 | ||
342 | install_handler((unsigned)irq_exception_entry, |
325 | install_handler((unsigned) irq_exception_entry, |
343 | (unsigned*)EXC_IRQ_VEC); |
326 | (unsigned *) EXC_IRQ_VEC); |
344 | 327 | ||
345 | install_handler((unsigned)fiq_exception_entry, |
328 | install_handler((unsigned)fiq_exception_entry, |
346 | (unsigned*)EXC_FIQ_VEC); |
329 | (unsigned *) EXC_FIQ_VEC); |
347 | } |
330 | } |
348 | 331 | ||
349 | - | ||
350 | #ifdef HIGH_EXCEPTION_VECTORS |
332 | #ifdef HIGH_EXCEPTION_VECTORS |
351 | /** Activates use of high exception vectors addresses. */ |
333 | /** Activates use of high exception vectors addresses. */ |
352 | static void high_vectors() |
334 | static void high_vectors(void) |
353 | { |
335 | { |
354 | uint32_t control_reg; |
336 | uint32_t control_reg; |
355 | 337 | ||
356 | asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg)); |
338 | asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg)); |
357 | 339 | ||
358 | //switch on the high vectors bit |
340 | /* switch on the high vectors bit */ |
359 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
341 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
360 | 342 | ||
361 | asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
343 | asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
362 | } |
344 | } |
363 | #endif |
345 | #endif |
364 | 346 | ||
365 | - | ||
366 | /** Initializes exception handling. |
347 | /** Initializes exception handling. |
367 | * |
348 | * |
368 | * Installs low-level exception handlers and then registers |
349 | * Installs low-level exception handlers and then registers |
369 | * exceptions and their handlers to kernel exception dispatcher. |
350 | * exceptions and their handlers to kernel exception dispatcher. |
370 | */ |
351 | */ |
371 | void exception_init(void) |
352 | void exception_init(void) |
372 | { |
353 | { |
373 | #ifdef HIGH_EXCEPTION_VECTORS |
354 | #ifdef HIGH_EXCEPTION_VECTORS |
374 | high_vectors(); |
355 | high_vectors(); |
375 | #endif |
356 | #endif |
376 | install_exception_handlers(); |
357 | install_exception_handlers(); |
377 | 358 | ||
378 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
359 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
379 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort); |
360 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", |
- | 361 | (iroutine) prefetch_abort); |
|
380 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
362 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
381 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
363 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
382 | } |
364 | } |
383 | 365 | ||
384 | - | ||
385 | /** Prints #istate_t structure content. |
366 | /** Prints #istate_t structure content. |
386 | * |
367 | * |
387 | * @param istate Structure to be printed. |
368 | * @param istate Structure to be printed. |
388 | */ |
369 | */ |
389 | void print_istate(istate_t *istate) |
370 | void print_istate(istate_t *istate) |
390 | { |
371 | { |
391 | dprintf("istate dump:\n"); |
372 | dprintf("istate dump:\n"); |
392 | 373 | ||
393 | dprintf(" r0: %x r1: %x r2: %x r3: %x\n", |
374 | dprintf(" r0: %x r1: %x r2: %x r3: %x\n", |
394 | istate->r0, istate->r1, istate->r2, istate->r3); |
375 | istate->r0, istate->r1, istate->r2, istate->r3); |
395 | dprintf(" r4: %x r5: %x r6: %x r7: %x\n", |
376 | dprintf(" r4: %x r5: %x r6: %x r7: %x\n", |
396 | istate->r4, istate->r5, istate->r6, istate->r7); |
377 | istate->r4, istate->r5, istate->r6, istate->r7); |
397 | dprintf(" r8: %x r8: %x r10: %x r11: %x\n", |
378 | dprintf(" r8: %x r8: %x r10: %x r11: %x\n", |
398 | istate->r8, istate->r9, istate->r10, istate->r11); |
379 | istate->r8, istate->r9, istate->r10, istate->r11); |
399 | dprintf(" r12: %x sp: %x lr: %x spsr: %x\n", |
380 | dprintf(" r12: %x sp: %x lr: %x spsr: %x\n", |
400 | istate->r12, istate->sp, istate->lr, istate->spsr); |
381 | istate->r12, istate->sp, istate->lr, istate->spsr); |
401 | 382 | ||
402 | dprintf(" pc: %x\n", istate->pc); |
383 | dprintf(" pc: %x\n", istate->pc); |
403 | } |
384 | } |
404 | 385 | ||
405 | - | ||
406 | /** @} |
386 | /** @} |
407 | */ |
387 | */ |
408 | 388 |