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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32mm |
29 | /** @addtogroup arm32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_arm32_PAGE_H_ |
35 | #ifndef KERN_arm32_PAGE_H_ |
36 | #define KERN_arm32_PAGE_H_ |
36 | #define KERN_arm32_PAGE_H_ |
37 | 37 | ||
38 | #include <arch/mm/frame.h> |
38 | #include <arch/mm/frame.h> |
39 | #include <mm/mm.h> |
39 | #include <mm/mm.h> |
40 | #include <arch/exception.h> |
40 | #include <arch/exception.h> |
41 | 41 | ||
42 | 42 | ||
43 | #define PAGE_WIDTH FRAME_WIDTH |
43 | #define PAGE_WIDTH FRAME_WIDTH |
44 | #define PAGE_SIZE FRAME_SIZE |
44 | #define PAGE_SIZE FRAME_SIZE |
45 | 45 | ||
46 | #define PAGE_COLOR_BITS 0 /* dummy */ |
46 | #define PAGE_COLOR_BITS 0 /* dummy */ |
47 | 47 | ||
48 | #ifndef __ASM__ |
48 | #ifndef __ASM__ |
49 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
49 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
50 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
50 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
51 | #else |
51 | #else |
52 | # define KA2PA(x) ((x) - 0x80000000) |
52 | # define KA2PA(x) ((x) - 0x80000000) |
53 | # define PA2KA(x) ((x) + 0x80000000) |
53 | # define PA2KA(x) ((x) + 0x80000000) |
54 | #endif |
54 | #endif |
55 | 55 | ||
56 | #ifdef KERNEL |
56 | #ifdef KERNEL |
57 | 57 | ||
58 | #define PTL0_ENTRIES_ARCH (2<<12) // 4096 |
58 | #define PTL0_ENTRIES_ARCH (2<<12) // 4096 |
59 | #define PTL1_ENTRIES_ARCH 0 |
59 | #define PTL1_ENTRIES_ARCH 0 |
60 | #define PTL2_ENTRIES_ARCH 0 |
60 | #define PTL2_ENTRIES_ARCH 0 |
61 | /* coarse page tables used (256*4 = 1KB per page) */ |
61 | /* coarse page tables used (256*4 = 1KB per page) */ |
62 | #define PTL3_ENTRIES_ARCH (2<<8) // 256 |
62 | #define PTL3_ENTRIES_ARCH (2<<8) // 256 |
63 | 63 | ||
64 | #define PTL0_SIZE_ARCH FOUR_FRAMES |
64 | #define PTL0_SIZE_ARCH FOUR_FRAMES |
65 | #define PTL1_SIZE_ARCH 0 |
65 | #define PTL1_SIZE_ARCH 0 |
66 | #define PTL2_SIZE_ARCH 0 |
66 | #define PTL2_SIZE_ARCH 0 |
67 | #define PTL3_SIZE_ARCH ONE_FRAME |
67 | #define PTL3_SIZE_ARCH ONE_FRAME |
68 | 68 | ||
69 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
69 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
70 | #define PTL1_INDEX_ARCH(vaddr) 0 |
70 | #define PTL1_INDEX_ARCH(vaddr) 0 |
71 | #define PTL2_INDEX_ARCH(vaddr) 0 |
71 | #define PTL2_INDEX_ARCH(vaddr) 0 |
72 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
72 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
73 | 73 | ||
74 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 )) |
74 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 )) |
75 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
75 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
76 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
76 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
77 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 )) |
77 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 )) |
78 | 78 | ||
79 | #define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0))) |
79 | #define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0))) |
80 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10) |
80 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10) |
81 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
81 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
82 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
82 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
83 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12) |
83 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12) |
84 | 84 | ||
85 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i)) |
85 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i)) |
86 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
86 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
87 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
87 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
88 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i)) |
88 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i)) |
89 | 89 | ||
90 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x)) |
90 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x)) |
91 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
91 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
92 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
92 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
93 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x)) |
93 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x)) |
94 | 94 | ||
95 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
95 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
96 | // TODO: ?? != 0 |
96 | // TODO: ?? != 0 |
97 | #define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 ) |
97 | #define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 ) |
98 | 98 | ||
99 | /* pte should point into ptl3 */ |
99 | /* pte should point into ptl3 */ |
100 | #define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) |
100 | #define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) |
101 | /* pte should point into ptl3 */ |
101 | /* pte should point into ptl3 */ |
102 | #define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW ) |
102 | #define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW ) |
103 | 103 | ||
104 | #define PTE_EXECUTABLE_ARCH(pte) 1 |
104 | #define PTE_EXECUTABLE_ARCH(pte) 1 |
105 | 105 | ||
106 | #ifndef __ASM__ |
106 | #ifndef __ASM__ |
107 | 107 | ||
108 | /** |
108 | /** |
109 | * Sets the address of level 0 page table. |
109 | * Sets the address of level 0 page table. |
110 | * |
110 | * |
111 | * \param pt pointer to the page table to set |
111 | * \param pt pointer to the page table to set |
112 | */ |
112 | */ |
113 | static inline void set_ptl0_addr( pte_level0_t* pt) |
113 | static inline void set_ptl0_addr( pte_level0_t* pt) |
114 | { |
114 | { |
115 | asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n" |
115 | asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n" |
116 | : |
116 | : |
117 | : "r"(pt) |
117 | : "r"(pt) |
118 | ); |
118 | ); |
119 | 119 | ||
120 | } |
120 | } |
121 | 121 | ||
122 | /** |
122 | /** |
123 | * Returns level 0 page table entry flags. |
123 | * Returns level 0 page table entry flags. |
124 | * |
124 | * |
125 | * \param pt level 0 page table |
125 | * \param pt level 0 page table |
126 | * \param i index of the entry to return |
126 | * \param i index of the entry to return |
127 | */ |
127 | */ |
128 | static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
128 | static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
129 | { |
129 | { |
130 | pte_level0_t *p = &pt[i]; |
130 | pte_level0_t *p = &pt[i]; |
131 | 131 | ||
132 | return |
132 | return |
133 | ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) | |
133 | ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) | |
134 | ( 1 << PAGE_USER_SHIFT ) | |
134 | ( 1 << PAGE_USER_SHIFT ) | |
135 | ( 1 << PAGE_READ_SHIFT ) | |
135 | ( 1 << PAGE_READ_SHIFT ) | |
136 | ( 1 << PAGE_WRITE_SHIFT ) | |
136 | ( 1 << PAGE_WRITE_SHIFT ) | |
137 | ( 1 << PAGE_EXEC_SHIFT ) | |
137 | ( 1 << PAGE_EXEC_SHIFT ) | |
138 | ( 1 << PAGE_CACHEABLE_SHIFT ) |
138 | ( 1 << PAGE_CACHEABLE_SHIFT ) |
139 | ; |
139 | ; |
140 | } |
140 | } |
141 | 141 | ||
142 | /** |
142 | /** |
143 | * Returns level 1 page table entry flags. |
143 | * Returns level 1 page table entry flags. |
144 | * |
144 | * |
145 | * \param pt level 1 page table |
145 | * \param pt level 1 page table |
146 | * \param i index of the entry to return |
146 | * \param i index of the entry to return |
147 | */ |
147 | */ |
148 | static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
148 | static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
149 | { |
149 | { |
150 | pte_level1_t *p = &pt[i]; |
150 | pte_level1_t *p = &pt[i]; |
151 | 151 | ||
152 | return |
152 | return |
153 | ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | |
153 | ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | |
154 | ( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) | |
154 | ( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) | |
155 | ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) | |
155 | ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) | |
156 | ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) | |
156 | ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) | |
157 | ( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) | |
157 | ( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) | |
158 | ( 1 << PAGE_EXEC_SHIFT ) | |
158 | ( 1 << PAGE_EXEC_SHIFT ) | |
159 | ( p->bufferable << PAGE_CACHEABLE ) |
159 | ( p->bufferable << PAGE_CACHEABLE ) |
160 | ; |
160 | ; |
161 | } |
161 | } |
162 | 162 | ||
163 | /** |
163 | /** |
164 | * Sets flags of level 0 page table entry. |
164 | * Sets flags of level 0 page table entry. |
165 | * |
165 | * |
166 | * \param pt level 0 page table |
166 | * \param pt level 0 page table |
167 | * \param i index of the entry to be changed |
167 | * \param i index of the entry to be changed |
168 | * \param flags new flags |
168 | * \param flags new flags |
169 | * |
169 | * |
170 | * TODO: why should_be_zero set to 1? |
170 | * TODO: why should_be_zero set to 1? |
171 | */ |
171 | */ |
172 | static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
172 | static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
173 | { |
173 | { |
174 | pte_level0_t *p = &pt[i]; |
174 | pte_level0_t *p = &pt[i]; |
175 | 175 | ||
176 | if (flags & PAGE_NOT_PRESENT) { |
176 | if (flags & PAGE_NOT_PRESENT) { |
177 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
177 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
178 | // p->should_be_zero = 1; |
178 | // p->should_be_zero = 1; |
179 | } else { |
179 | } else { |
180 | p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; |
180 | p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; |
181 | // p->should_be_zero = 0; |
181 | // p->should_be_zero = 0; |
182 | } |
182 | } |
183 | } |
183 | } |
184 | 184 | ||
185 | /** |
185 | /** |
186 | * Sets flags of level 1 page table entry. |
186 | * Sets flags of level 1 page table entry. |
187 | * |
187 | * |
188 | * We use same access rights for the whole page. When page is not preset then |
188 | * We use same access rights for the whole page. When page is not preset then |
189 | * store 1 in acess_rigts_3. |
189 | * store 1 in acess_rigts_3. |
190 | * TODO: why access_right_3? |
190 | * TODO: why access_right_3? |
191 | * |
191 | * |
192 | * \param pt level 1 page table |
192 | * \param pt level 1 page table |
193 | * \param i index of the entry to be changed |
193 | * \param i index of the entry to be changed |
194 | * \param flags new flags |
194 | * \param flags new flags |
195 | */ |
195 | */ |
196 | static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
196 | static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
197 | { |
197 | { |
198 | pte_level1_t *p = &pt[i]; |
198 | pte_level1_t *p = &pt[i]; |
199 | 199 | ||
200 | if (flags & PAGE_NOT_PRESENT) { |
200 | if (flags & PAGE_NOT_PRESENT) { |
201 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
201 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
202 | // p->access_permission_3 = 1; |
202 | // p->access_permission_3 = 1; |
203 | } else { |
203 | } else { |
204 | p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; |
204 | p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; |
205 | // p->access_permission_3 = p->access_permission_0; |
205 | // p->access_permission_3 = p->access_permission_0; |
206 | } |
206 | } |
207 | 207 | ||
208 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
208 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
209 | 209 | ||
210 | /* default access permission */ |
210 | /* default access permission */ |
211 | p->access_permission_0 = p->access_permission_1 = |
211 | p->access_permission_0 = p->access_permission_1 = |
212 | p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW; |
212 | p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW; |
213 | 213 | ||
214 | if (flags & PAGE_USER) { |
214 | if (flags & PAGE_USER) { |
215 | if (flags & PAGE_READ) { |
215 | if (flags & PAGE_READ) { |
216 | p->access_permission_0 = p->access_permission_1 = |
216 | p->access_permission_0 = p->access_permission_1 = |
217 | p->access_permission_2 = p->access_permission_3 = |
217 | p->access_permission_2 = p->access_permission_3 = |
218 | PTE_AP_USER_RO_KERNEL_RW; |
218 | PTE_AP_USER_RO_KERNEL_RW; |
219 | } |
219 | } |
220 | if (flags & PAGE_WRITE) { |
220 | if (flags & PAGE_WRITE) { |
221 | p->access_permission_0 = p->access_permission_1 = |
221 | p->access_permission_0 = p->access_permission_1 = |
222 | p->access_permission_2 = p->access_permission_3 = |
222 | p->access_permission_2 = p->access_permission_3 = |
223 | PTE_AP_USER_RW_KERNEL_RW; |
223 | PTE_AP_USER_RW_KERNEL_RW; |
224 | } |
224 | } |
225 | } |
225 | } |
226 | } |
226 | } |
227 | 227 | ||
- | 228 | ||
228 | extern void page_arch_init(void); |
229 | extern void page_arch_init(void); |
229 | 230 | ||
- | 231 | extern void prefetch_abourt(int n, istate_t *istate); |
|
- | 232 | extern void data_abourt(int n, istate_t *istate); |
|
- | 233 | ||
230 | #endif /* __ASM__ */ |
234 | #endif /* __ASM__ */ |
231 | 235 | ||
232 | #endif /* KERNEL */ |
236 | #endif /* KERNEL */ |
233 | 237 | ||
234 | #endif |
238 | #endif |
235 | 239 | ||
236 | /** @} |
240 | /** @} |
237 | */ |
241 | */ |
238 | 242 | ||
239 | 243 |