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#
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#
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# Copyright (C) 2006 Martin Decky
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# Copyright (C) 2006 Martin Decky
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# All rights reserved.
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# All rights reserved.
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#
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#
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# Redistribution and use in source and binary forms, with or without
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# modification, are permitted provided that the following conditions
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# are met:
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# are met:
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#
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#
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# - Redistributions of source code must retain the above copyright
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#   derived from this software without specific prior written permission.
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#
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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#include "asm.h"
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#include "asm.h"
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#include "regname.h"
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#include "regname.h"
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#include "debug.inc"
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#include "debug.inc"
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.text
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.text
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.global halt
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.global halt
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.global memcpy
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.global memcpy
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.global jump_to_kernel
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.global jump_to_kernel
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halt:
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halt:
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	b halt
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	b halt
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memcpy:
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memcpy:
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	srwi. r7, r5, 3
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	srwi. r7, r5, 3
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	addi r6, r3, -4
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	addi r6, r3, -4
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	addi r4, r4, -4
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	addi r4, r4, -4
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	beq	2f
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	beq	2f
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47
	
48
	andi. r0, r6, 3
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	andi. r0, r6, 3
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	mtctr r7
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	mtctr r7
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	bne 5f
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	bne 5f
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51
	
52
	1:
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	1:
53
	
53
	
54
	lwz r7, 4(r4)
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	lwz r7, 4(r4)
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	lwzu r8, 8(r4)
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	lwzu r8, 8(r4)
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	stw r7, 4(r6)
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	stw r7, 4(r6)
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	stwu r8, 8(r6)
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	stwu r8, 8(r6)
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	bdnz 1b
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	bdnz 1b
59
	
59
	
60
	andi. r5, r5, 7
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	andi. r5, r5, 7
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61
	
62
	2:
62
	2:
63
	
63
	
64
	cmplwi 0, r5, 4
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	cmplwi 0, r5, 4
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	blt 3f
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	blt 3f
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66
	
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	lwzu r0, 4(r4)
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	lwzu r0, 4(r4)
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	addi r5, r5, -4
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	addi r5, r5, -4
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	stwu r0, 4(r6)
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	stwu r0, 4(r6)
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70
	
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	3:
71
	3:
72
	
72
	
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	cmpwi 0, r5, 0
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	cmpwi 0, r5, 0
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	beqlr
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	beqlr
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	mtctr r5
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	mtctr r5
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	addi r4, r4, 3
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	addi r4, r4, 3
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	addi r6, r6, 3
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	addi r6, r6, 3
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78
	
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	4:
79
	4:
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	lbzu r0, 1(r4)
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	lbzu r0, 1(r4)
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	stbu r0, 1(r6)
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	stbu r0, 1(r6)
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	bdnz 4b
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	bdnz 4b
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	blr
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	blr
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85
	
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	5:
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	5:
87
	
87
	
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	subfic r0, r0, 4
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	subfic r0, r0, 4
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	mtctr r0
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	mtctr r0
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90
	
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	6:
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	6:
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92
	
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	lbz r7, 4(r4)
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	lbz r7, 4(r4)
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	addi r4, r4, 1
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	addi r4, r4, 1
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	stb r7, 4(r6)
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	stb r7, 4(r6)
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	addi r6, r6, 1
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	addi r6, r6, 1
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	bdnz 6b
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	bdnz 6b
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	subf r5, r0, r5
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	subf r5, r0, r5
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	rlwinm. r7, r5, 32-3, 3, 31
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	rlwinm. r7, r5, 32-3, 3, 31
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	beq 2b
100
	beq 2b
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	mtctr r7
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	mtctr r7
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	b 1b
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	b 1b
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104
 
104
 
105
jump_to_kernel:
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jump_to_kernel:
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106
	
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	# r3 = bootinfo (pa)
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	# r3 = bootinfo (pa)
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	# r4 = bootinfo_size
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	# r4 = bootinfo_size
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	# r5 = trans (pa)
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	# r5 = trans (pa)
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	# r6 = bytes to copy
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	# r6 = bytes to copy
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	# r7 = real_mode (pa)
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	# r7 = real_mode (pa)
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	# r8 = framebuffer (pa)
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	# r8 = framebuffer (pa)
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	# r9 = scanline
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	# r9 = scanline
114
	
114
	
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	# disable interrupts
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	# disable interrupts
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116
	
117
	mfmsr r31
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	mfmsr r31
118
	rlwinm r31, r31, 0, 17, 15
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	rlwinm r31, r31, 0, 17, 15
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	mtmsr r31
119
	mtmsr r31
120
	
120
	
121
	# set real_mode meeting point address
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	# set real_mode meeting point address
122
	
122
	
123
	mtspr srr0, r7
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	mtspr srr0, r7
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124
	
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	# jumps to real_mode
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	# jumps to real_mode
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126
	
127
	mfmsr r31
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	mfmsr r31
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	lis r30, ~0@h
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	lis r30, ~0@h
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	ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
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	ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
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	and r31, r31, r30
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	and r31, r31, r30
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	mtspr srr1, r31
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	mtspr srr1, r31
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132
	
133
	sync
133
	sync
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	isync
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	isync
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	rfi
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	rfi
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.section REALMODE, "ax"
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.section REALMODE, "ax"
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.align PAGE_WIDTH
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.align PAGE_WIDTH
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.global real_mode
139
.global real_mode
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140
 
141
real_mode:
141
real_mode:
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142
	
-
 
143
	DEBUG_INIT
143
	DEBUG_real_mode
144
	DEBUG_real_mode
144
	
145
	
145
	# copy kernel to proper location
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	# copy kernel to proper location
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	#
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	#
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	# r5 = trans (pa)
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	# r5 = trans (pa)
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	# r6 = bytes to copy
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	# r6 = bytes to copy
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	# r8 = framebuffer (pa)
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	# r8 = framebuffer (pa)
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	# r9 = scanline
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	# r9 = scanline
151
	
152
	
152
	li r31, PAGE_SIZE >> 2
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	li r31, PAGE_SIZE >> 2
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	li r30, 0
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	li r30, 0
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	page_copy:
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	page_copy:
156
		
157
		
157
		cmpwi r6, 0
158
		cmpwi r6, 0
158
		beq copy_end
159
		beq copy_end
159
		
160
		
160
		# copy page
161
		# copy page
161
		
162
		
162
		mtctr r31
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		mtctr r31
163
		lwz r29, 0(r5)
164
		lwz r29, 0(r5)
164
		
165
		
-
 
166
		DEBUG_INIT
-
 
167
		DEBUG_copy_loop
-
 
168
		
165
		copy_loop:
169
		copy_loop:
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170
			
167
			lwz r28, 0(r29)
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			lwz r28, 0(r29)
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			stw r28, 0(r30)
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			stw r28, 0(r30)
169
			
173
			
170
			addi r29, r29, 4
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			addi r29, r29, 4
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			addi r30, r30, 4
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			addi r30, r30, 4
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			subi r6, r6, 4
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			subi r6, r6, 4
173
			
177
			
174
			cmpwi r6, 0
178
			cmpwi r6, 0
175
			beq copy_end
179
			beq copy_end
176
			
180
			
177
			bdnz copy_loop
181
			bdnz copy_loop
178
		
182
			
-
 
183
			DEBUG_end_copy_loop
-
 
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179
		addi r5, r5, 4
185
		addi r5, r5, 4
180
		b page_copy
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		b page_copy
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187
	
182
	copy_end:
188
	copy_end:
183
	
189
	
-
 
190
	DEBUG_segments
-
 
191
	
184
	# initially fill segment registers
192
	# initially fill segment registers
185
 
193
 
186
	li r31, 16
194
	li r31, 16
187
	mtctr r31
195
	mtctr r31
188
	li r31, 0
196
	li r31, 0
189
	li r30, 0x2000
197
	li r30, 0x2000
190
 
198
 
191
	seg_fill:
199
	seg_fill:
192
	
200
	
193
		mtsrin r30, r31
201
		mtsrin r30, r31
194
		addi r30, r30, 0x111
202
		addi r30, r30, 0x111
195
		addis r31, r31, 0x1000    # move to next SR
203
		addis r31, r31, 0x1000    # move to next SR
196
		
204
		
197
		bdnz seg_fill
205
		bdnz seg_fill
198
	
206
	
199
	# invalidate block address translation registers
207
	# invalidate block address translation registers
200
	
208
	
-
 
209
	DEBUG_bat
-
 
210
	
201
	li r30, 0
211
	li r30, 0
202
	
212
	
203
	mtspr ibat0u, r30
213
	mtspr ibat0u, r30
204
	mtspr ibat0l, r30
214
	mtspr ibat0l, r30
205
	
215
	
206
	mtspr ibat1u, r30
216
	mtspr ibat1u, r30
207
	mtspr ibat1l, r30
217
	mtspr ibat1l, r30
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218
	
209
	mtspr ibat2u, r30
219
	mtspr ibat2u, r30
210
	mtspr ibat2l, r30
220
	mtspr ibat2l, r30
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212
	mtspr ibat3u, r30
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	mtspr ibat3u, r30
213
	mtspr ibat3l, r30
223
	mtspr ibat3l, r30
214
	
224
	
215
	mtspr dbat0u, r30
225
	mtspr dbat0u, r30
216
	mtspr dbat0l, r30
226
	mtspr dbat0l, r30
217
	
227
	
218
	mtspr dbat1u, r30
228
	mtspr dbat1u, r30
219
	mtspr dbat1l, r30
229
	mtspr dbat1l, r30
220
	
230
	
221
	mtspr dbat2u, r30
231
	mtspr dbat2u, r30
222
	mtspr dbat2l, r30
232
	mtspr dbat2l, r30
223
	
233
	
224
	mtspr dbat3u, r30
234
	mtspr dbat3u, r30
225
	mtspr dbat3l, r30
235
	mtspr dbat3l, r30
226
	
236
	
227
	# create identity mapping
237
	# create identity mapping
228
	
238
	
-
 
239
	DEBUG_mapping
-
 
240
	
229
	# FIXME: map exactly the size of RAM
241
	# FIXME: map exactly the size of RAM
230
	
242
	
231
	lis r31, 0x8000
243
	lis r31, 0x8000
232
	ori r31, r31, 0x0ffe
244
	ori r31, r31, 0x0ffe
233
	
245
	
234
	lis r30, 0x0000
246
	lis r30, 0x0000
235
	ori r30, r30, 0x0002
247
	ori r30, r30, 0x0002
236
	
248
	
237
	mtspr ibat0u, r31
249
	mtspr ibat0u, r31
238
	mtspr ibat0l, r30
250
	mtspr ibat0l, r30
239
	
251
	
240
	mtspr dbat0u, r31
252
	mtspr dbat0u, r31
241
	mtspr dbat0l, r30
253
	mtspr dbat0l, r30
242
	
254
	
-
 
255
	DEBUG_tlb
-
 
256
	
243
	tlbia
257
	tlbia
244
	tlbsync
258
	tlbsync
245
	
259
	
-
 
260
	DEBUG_prepare
-
 
261
	
246
	# start the kernel
262
	# start the kernel
247
	#
263
	#
248
	# r3 = bootinfo (pa)
264
	# r3 = bootinfo (pa)
249
	
265
	
250
	lis r31, KERNEL_START_ADDR@ha
266
	lis r31, KERNEL_START_ADDR@ha
251
	addi r31, r31, KERNEL_START_ADDR@l
267
	addi r31, r31, KERNEL_START_ADDR@l
252
	
268
	
253
	mtspr srr0, r31
269
	mtspr srr0, r31
254
	
270
	
255
	mfmsr r31
271
	mfmsr r31
256
	ori r31, r31, (msr_ir | msr_dr)@l
272
	ori r31, r31, (msr_ir | msr_dr)@l
257
	mtspr srr1, r31
273
	mtspr srr1, r31
258
	
274
	
259
	sync
275
	sync
260
	isync
276
	isync
261
	
277
	
262
	DEBUG_rfi
278
	DEBUG_rfi
263
	rfi
279
	rfi
264
 
280
 
265
.align PAGE_WIDTH
281
.align PAGE_WIDTH
266
.global trans
282
.global trans
267
trans:
283
trans:
268
	.space (TRANS_SIZE * TRANS_ITEM_SIZE)
284
	.space (TRANS_SIZE * TRANS_ITEM_SIZE)
269
 
285