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1 | # |
1 | # |
2 | # Copyright (C) 2006 Martin Decky |
2 | # Copyright (C) 2006 Martin Decky |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include "asm.h" |
29 | #include "asm.h" |
30 | #include "regname.h" |
30 | #include "regname.h" |
31 | 31 | ||
32 | .data |
32 | .data |
33 | 33 | ||
34 | flush_buffer: |
34 | flush_buffer: |
35 | .space (L1_CACHE_LINES * L1_CACHE_BYTES) |
35 | .space (L1_CACHE_LINES * L1_CACHE_BYTES) |
36 | 36 | ||
37 | .text |
37 | .text |
38 | 38 | ||
39 | .global halt |
39 | .global halt |
40 | .global jump_to_kernel |
40 | .global jump_to_kernel |
41 | 41 | ||
42 | halt: |
42 | halt: |
43 | b halt |
43 | b halt |
44 | 44 | ||
45 | jump_to_kernel: |
45 | jump_to_kernel: |
46 | 46 | ||
47 | # r3 = memmap (pa) |
47 | # r3 = memmap (pa) |
48 | # r4 = trans (pa) |
48 | # r4 = trans (pa) |
49 | # r5 = kernel size |
49 | # r5 = kernel size |
50 | # r6 = real_mode (pa) |
50 | # r6 = real_mode (pa) |
51 | 51 | ||
52 | mtspr srr0, r6 |
52 | mtspr srr0, r6 |
53 | 53 | ||
54 | # jumps to real_mode |
54 | # jumps to real_mode |
55 | 55 | ||
56 | mfmsr r31 |
56 | mfmsr r31 |
57 | lis r30, ~0@h |
57 | lis r30, ~0@h |
58 | ori r30, r30, ~(msr_ir | msr_dr)@l |
58 | ori r30, r30, ~(msr_ir | msr_dr)@l |
59 | and r31, r31, r30 |
59 | and r31, r31, r30 |
60 | mtspr srr1, r31 |
60 | mtspr srr1, r31 |
61 | rfi |
61 | rfi |
62 | 62 | ||
63 | .section REALMODE |
63 | .section REALMODE |
64 | .align PAGE_WIDTH |
64 | .align PAGE_WIDTH |
65 | .global real_mode |
65 | .global real_mode |
66 | 66 | ||
67 | real_mode: |
67 | real_mode: |
68 | 68 | ||
69 | # copy kernel to proper location |
69 | # copy kernel to proper location |
70 | # |
70 | # |
71 | # r4 = trans (pa) |
71 | # r4 = trans (pa) |
72 | # r5 = kernel size |
72 | # r5 = kernel size |
73 | 73 | ||
74 | li r31, PAGE_SIZE >> 2 |
74 | li r31, PAGE_SIZE >> 2 |
75 | li r30, 0 |
75 | li r30, 0 |
76 | 76 | ||
77 | page_copy: |
77 | page_copy: |
78 | 78 | ||
79 | cmpwi r5, 0 |
79 | cmpwi r5, 0 |
80 | beq copy_end |
80 | beq copy_end |
81 | 81 | ||
82 | # copy page |
82 | # copy page |
83 | 83 | ||
84 | mtctr r31 |
84 | mtctr r31 |
85 | lwz r29, 0(r4) |
85 | lwz r29, 0(r4) |
86 | 86 | ||
87 | copy_loop: |
87 | copy_loop: |
88 | 88 | ||
89 | lwz r28, 0(r29) |
89 | lwz r28, 0(r29) |
90 | stw r28, 0(r30) |
90 | stw r28, 0(r30) |
91 | 91 | ||
92 | addi r29, r29, 4 |
92 | addi r29, r29, 4 |
93 | addi r30, r30, 4 |
93 | addi r30, r30, 4 |
94 | subi r5, r5, 4 |
94 | subi r5, r5, 4 |
95 | 95 | ||
96 | cmpwi r5, 0 |
96 | cmpwi r5, 0 |
97 | beq copy_end |
97 | beq copy_end |
98 | 98 | ||
99 | bdnz copy_loop |
99 | bdnz copy_loop |
100 | 100 | ||
101 | addi r4, r4, 4 |
101 | addi r4, r4, 4 |
102 | b page_copy |
102 | b page_copy |
103 | 103 | ||
104 | copy_end: |
104 | copy_end: |
105 | 105 | ||
106 | # invalidate segment registers |
106 | # invalidate segment registers |
107 | 107 | ||
108 | # li r31, 16 |
108 | li r31, 16 |
109 | # mtctr r31 |
109 | mtctr r31 |
110 | # li r31, 0 |
110 | li r31, 0 |
111 | # li r30, 0 |
111 | li r30, 0 |
112 | 112 | ||
113 | seg_fill: |
113 | seg_fill: |
114 | 114 | ||
115 | # mtsrin r30, r31 |
115 | mtsrin r30, r31 |
116 | # addis r31, r31, 0x1000 # move to next SR |
116 | addis r31, r31, 0x1000 # move to next SR |
117 | # |
117 | |
118 | # bdnz seg_fill |
118 | bdnz seg_fill |
119 | 119 | ||
120 | # invalidate block address translation registers |
120 | # invalidate block address translation registers |
121 | 121 | ||
122 | mtspr ibat0u, r30 |
122 | mtspr ibat0u, r30 |
123 | mtspr ibat0l, r30 |
123 | mtspr ibat0l, r30 |
124 | 124 | ||
125 | mtspr ibat1u, r30 |
125 | mtspr ibat1u, r30 |
126 | mtspr ibat1l, r30 |
126 | mtspr ibat1l, r30 |
127 | 127 | ||
128 | mtspr ibat2u, r30 |
128 | mtspr ibat2u, r30 |
129 | mtspr ibat2l, r30 |
129 | mtspr ibat2l, r30 |
130 | 130 | ||
131 | mtspr ibat3u, r30 |
131 | mtspr ibat3u, r30 |
132 | mtspr ibat3l, r30 |
132 | mtspr ibat3l, r30 |
133 | 133 | ||
134 | mtspr dbat0u, r30 |
134 | mtspr dbat0u, r30 |
135 | mtspr dbat0l, r30 |
135 | mtspr dbat0l, r30 |
136 | 136 | ||
137 | mtspr dbat1u, r30 |
137 | mtspr dbat1u, r30 |
138 | mtspr dbat1l, r30 |
138 | mtspr dbat1l, r30 |
139 | 139 | ||
140 | mtspr dbat2u, r30 |
140 | mtspr dbat2u, r30 |
141 | mtspr dbat2l, r30 |
141 | mtspr dbat2l, r30 |
142 | 142 | ||
143 | mtspr dbat3u, r30 |
143 | mtspr dbat3u, r30 |
144 | mtspr dbat3l, r30 |
144 | mtspr dbat3l, r30 |
145 | 145 | ||
146 | # create identity mapping |
146 | # create identity mapping |
147 | 147 | ||
148 | # FIXME: map exactly the size of RAM |
148 | # FIXME: map exactly the size of RAM |
149 | 149 | ||
150 | lis r31, 0x8000 |
150 | lis r31, 0x8000 |
151 | ori r31, r31, 0x0ffe |
151 | ori r31, r31, 0x0ffe |
152 | 152 | ||
153 | lis r30, 0x0000 |
153 | lis r30, 0x0000 |
154 | ori r30, r30, 0x0002 |
154 | ori r30, r30, 0x0002 |
155 | 155 | ||
156 | mtspr ibat0u, r31 |
156 | mtspr ibat0u, r31 |
157 | mtspr ibat0l, r30 |
157 | mtspr ibat0l, r30 |
158 | 158 | ||
159 | mtspr dbat0u, r31 |
159 | mtspr dbat0u, r31 |
160 | mtspr dbat0l, r30 |
160 | mtspr dbat0l, r30 |
161 | 161 | ||
162 | # FIXME: temporal framebuffer mapping |
162 | # FIXME: temporal framebuffer mapping |
163 | 163 | ||
164 | lis r31, 0xf000 |
164 | lis r31, 0xf000 |
165 | ori r31, r31, 0x0ffe |
165 | ori r31, r31, 0x0ffe |
166 | 166 | ||
167 | lis r30, 0x8400 |
167 | lis r30, 0x8400 |
168 | ori r30, r30, 0x0002 |
168 | ori r30, r30, 0x0002 |
169 | 169 | ||
170 | mtspr dbat1u, r31 |
170 | mtspr dbat1u, r31 |
171 | mtspr dbat1l, r30 |
171 | mtspr dbat1l, r30 |
172 | 172 | ||
173 | tlbia |
173 | tlbia |
174 | 174 | ||
175 | # start the kernel |
175 | # start the kernel |
176 | # |
176 | # |
177 | # r3 = memmap (pa) |
177 | # r3 = memmap (pa) |
178 | 178 | ||
179 | lis r31, KERNEL_START_ADDR@ha |
179 | lis r31, KERNEL_START_ADDR@ha |
180 | addi r31, r31, KERNEL_START_ADDR@l |
180 | addi r31, r31, KERNEL_START_ADDR@l |
181 | 181 | ||
182 | mtspr srr0, r31 |
182 | mtspr srr0, r31 |
183 | 183 | ||
184 | mfmsr r31 |
184 | mfmsr r31 |
185 | ori r31, r31, (msr_ir | msr_dr)@l |
185 | ori r31, r31, (msr_ir | msr_dr)@l |
186 | mtspr srr1, r31 |
186 | mtspr srr1, r31 |
187 | 187 | ||
188 | rfi |
188 | rfi |
189 | 189 | ||
190 | .align PAGE_WIDTH |
190 | .align PAGE_WIDTH |
191 | .global trans |
191 | .global trans |
192 | trans: |
192 | trans: |
193 | .space (TRANS_SIZE * TRANS_ITEM_SIZE) |
193 | .space (TRANS_SIZE * TRANS_ITEM_SIZE) |
194 | 194 |