WebSVN – HelenOS – Diff – /SPARTAN/trunk/arch/amd64/src/pm.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/pm.h>
#include <arch/mm/page.h>
#include <arch/types.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
 
#include <config.h>
 
#include <memstr.h>
#include <mm/heap.h>
#include <debug.h>
 
/*
 * There is no segmentation in long mode so we set up flat mode. In this
 * mode, we use, for each privilege level, two segments spanning the
 * whole memory. One is for code and one is for data.
 */
 
struct descriptor gdt[GDT_ITEMS] = {
    /* NULL descriptor */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* KTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 1,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* KDATA descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* UTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_USER,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 1,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* UDATA descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 1,
      .granularity = 1,
      .base_24_31  = 0 },
    /* KTEXT 32-bit protected, for protected mode before long mode */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 1,
      .granularity = 1,
      .base_24_31  = 0 },
    /* TSS descriptor - set up will be completed later,
     * on AMD64 it is 64-bit - 2 items in table */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
};
 
struct idescriptor idt[IDT_ITEMS];
 
struct ptr_16_64 gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
struct ptr_16_64 idtr = {.limit = sizeof(idt), .base= (__u64) idt };
 
static struct tss tss;
struct tss *tss_p = NULL;
 
 
 
 
void gdt_tss_setbase(struct descriptor *d, __address base)
{
    struct tss_descriptor *td = (struct tss_descriptor *) d;
 
    td->base_0_15 = base & 0xffff;
    td->base_16_23 = ((base) >> 16) & 0xff;
    td->base_24_31 = ((base) >> 24) & 0xff;
    td->base_32_63 = ((base) >> 32);
}
 
void gdt_tss_setlimit(struct descriptor *d, __u32 limit)
{
    struct tss_descriptor *td = (struct tss_descriptor *) d;
 
    td->limit_0_15 = limit & 0xffff;
    td->limit_16_19 = (limit >> 16) & 0xf;
}
 
void idt_setoffset(struct idescriptor *d, __address offset)
{
    /*
     * Offset is a linear address.
     */
    d->offset_0_15 = offset & 0xffff;
    d->offset_16_31 = offset >> 16 & 0xffff;
    d->offset_32_63 = offset >> 32;
}
 
void tss_initialize(struct tss *t)
{
    memsetb((__address) t, sizeof(struct tss), 0);
}
 
/*
 * This function takes care of proper setup of IDT and IDTR.
 */
void idt_init(void)
{
    struct idescriptor *d;
    int i;
 
    for (i = 0; i < IDT_ITEMS; i++) {
        d = &idt[i];
 
        d->unused = 0;
        d->selector = gdtselector(KTEXT_DES);
 
        d->present = 1;
        d->type = AR_INTERRUPT; /* masking interrupt */
 
        if (i == VECTOR_SYSCALL) {
            /*
             * The syscall interrupt gate must be calleable from userland.
             */
            d->dpl |= PL_USER;
        }
       
        idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
        trap_register(i, null_interrupt);
    }
    trap_register(13, gp_fault);
    trap_register( 7, nm_fault);
    trap_register(12, ss_fault);   
}
 
 
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
static void clean_IOPL_NT_flags(void)
{
    asm
    (
        "pushfq;"
        "pop %%rax;"
        "and $~(0x7000),%%rax;"
        "pushq %%rax;"
        "popfq;"
        :
        :
        :"%rax"
    );
}
 
/* Clean AM(18) flag in CR0 register */
static void clean_AM_flag(void)
{
    asm
    (
        "mov %%cr0,%%rax;"
        "and $~(0x40000),%%rax;"
        "mov %%rax,%%cr0;"
        :
        :
        :"%rax"
    );
}
 
void pm_init(void)
{
    struct descriptor *gdt_p = (struct descriptor *) gdtr.base;
    struct tss_descriptor *tss_desc;
 
    /*
     * Each CPU has its private GDT and TSS.
     * All CPUs share one IDT.
     */
 
    if (config.cpu_active == 1) {
        idt_init();
        /*
         * NOTE: bootstrap CPU has statically allocated TSS, because
         * the heap hasn't been initialized so far.
         */
        tss_p = &tss;
    }
    else {
        tss_p = (struct tss *) malloc(sizeof(struct tss));
        if (!tss_p)
            panic("could not allocate TSS\n");
    }
 
    tss_initialize(tss_p);
 
    tss_desc = (struct tss_descriptor *) (&gdt_p[TSS_DES]);
    tss_desc->present = 1;
    tss_desc->type = AR_TSS;
    tss_desc->dpl = PL_KERNEL;
   
    gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
    gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
 
    __asm__("lgdt %0" : : "m"(gdtr));
    __asm__("lidt %0" : : "m"(idtr));
    /*
     * As of this moment, the current CPU has its own GDT pointing
     * to its own TSS. We just need to load the TR register.
     */
    __asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));
   
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels */
    clean_AM_flag();          /* Disable alignment check */
}
 

Rev 332	Rev 406
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/pm.h>	29	#include <arch/pm.h>
30	#include <arch/mm/page.h>	30	#include <arch/mm/page.h>
31	#include <arch/types.h>	31	#include <arch/types.h>
32	#include <arch/interrupt.h>	32	#include <arch/interrupt.h>
33	#include <arch/asm.h>	33	#include <arch/asm.h>
34		34
35	#include <config.h>	35	#include <config.h>
36		36
37	#include <memstr.h>	37	#include <memstr.h>
38	#include <mm/heap.h>	38	#include <mm/heap.h>
39	#include <debug.h>	39	#include <debug.h>
40		40
41	/*	41	/*
42	* There is no segmentation in long mode so we set up flat mode. In this	42	* There is no segmentation in long mode so we set up flat mode. In this
43	* mode, we use, for each privilege level, two segments spanning the	43	* mode, we use, for each privilege level, two segments spanning the
44	* whole memory. One is for code and one is for data.	44	* whole memory. One is for code and one is for data.
45	*/	45	*/
46		46
47	struct descriptor gdt[GDT_ITEMS] = {	47	struct descriptor gdt[GDT_ITEMS] = {
48	/* NULL descriptor */	48	/* NULL descriptor */
49	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	49	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
50	/* KTEXT descriptor */	50	/* KTEXT descriptor */
51	{ .limit_0_15 = 0xffff,	51	{ .limit_0_15 = 0xffff,
52	.base_0_15 = 0,	52	.base_0_15 = 0,
53	.base_16_23 = 0,	53	.base_16_23 = 0,
54	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE ,	54	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE ,
55	.limit_16_19 = 0xf,	55	.limit_16_19 = 0xf,
56	.available = 0,	56	.available = 0,
57	.longmode = 1,	57	.longmode = 1,
58	.special = 0,	58	.special = 0,
59	.granularity = 1,	59	.granularity = 1,
60	.base_24_31 = 0 },	60	.base_24_31 = 0 },
61	/* KDATA descriptor */	61	/* KDATA descriptor */
62	{ .limit_0_15 = 0xffff,	62	{ .limit_0_15 = 0xffff,
63	.base_0_15 = 0,	63	.base_0_15 = 0,
64	.base_16_23 = 0,	64	.base_16_23 = 0,
65	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL,	65	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL,
66	.limit_16_19 = 0xf,	66	.limit_16_19 = 0xf,
67	.available = 0,	67	.available = 0,
68	.longmode = 0,	68	.longmode = 0,
69	.special = 0,	69	.special = 0,
70	.granularity = 1,	70	.granularity = 1,
71	.base_24_31 = 0 },	71	.base_24_31 = 0 },
72	/* UTEXT descriptor */	72	/* UTEXT descriptor */
73	{ .limit_0_15 = 0xffff,	73	{ .limit_0_15 = 0xffff,
74	.base_0_15 = 0,	74	.base_0_15 = 0,
75	.base_16_23 = 0,	75	.base_16_23 = 0,
76	.access = AR_PRESENT \| AR_CODE \| DPL_USER,	76	.access = AR_PRESENT \| AR_CODE \| DPL_USER,
77	.limit_16_19 = 0xf,	77	.limit_16_19 = 0xf,
78	.available = 0,	78	.available = 0,
79	.longmode = 1,	79	.longmode = 1,
80	.special = 0,	80	.special = 0,
81	.granularity = 1,	81	.granularity = 1,
82	.base_24_31 = 0 },	82	.base_24_31 = 0 },
83	/* UDATA descriptor */	83	/* UDATA descriptor */
84	{ .limit_0_15 = 0xffff,	84	{ .limit_0_15 = 0xffff,
85	.base_0_15 = 0,	85	.base_0_15 = 0,
86	.base_16_23 = 0,	86	.base_16_23 = 0,
87	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER,	87	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER,
88	.limit_16_19 = 0xf,	88	.limit_16_19 = 0xf,
89	.available = 0,	89	.available = 0,
90	.longmode = 0,	90	.longmode = 0,
91	.special = 1,	91	.special = 1,
92	.granularity = 1,	92	.granularity = 1,
93	.base_24_31 = 0 },	93	.base_24_31 = 0 },
94	/* KTEXT 32-bit protected, for protected mode before long mode */	94	/* KTEXT 32-bit protected, for protected mode before long mode */
95	{ .limit_0_15 = 0xffff,	95	{ .limit_0_15 = 0xffff,
96	.base_0_15 = 0,	96	.base_0_15 = 0,
97	.base_16_23 = 0,	97	.base_16_23 = 0,
98	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,	98	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,
99	.limit_16_19 = 0xf,	99	.limit_16_19 = 0xf,
100	.available = 0,	100	.available = 0,
101	.longmode = 0,	101	.longmode = 0,
102	.special = 1,	102	.special = 1,
103	.granularity = 1,	103	.granularity = 1,
104	.base_24_31 = 0 },	104	.base_24_31 = 0 },
105	/* TSS descriptor - set up will be completed later,	105	/* TSS descriptor - set up will be completed later,
106	* on AMD64 it is 64-bit - 2 items in table */	106	* on AMD64 it is 64-bit - 2 items in table */
107	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	107	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
108	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }	108	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
109	};	109	};
110		110
111	struct idescriptor idt[IDT_ITEMS];	111	struct idescriptor idt[IDT_ITEMS];
112		112
113	struct ptr_16_64 gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };	113	struct ptr_16_64 gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
114	struct ptr_16_64 idtr = {.limit = sizeof(idt), .base= (__u64) idt };	114	struct ptr_16_64 idtr = {.limit = sizeof(idt), .base= (__u64) idt };
115		115
116	static struct tss tss;	116	static struct tss tss;
117	struct tss *tss_p = NULL;	117	struct tss *tss_p = NULL;
118		118
119	/* TODO: Does not compile correctly if it does not exist ???? */	-
120	int __attribute__ ((section ("K_DATA_START"))) __fake;	-
121		-
122	void gdt_tss_setbase(struct descriptor *d, __address base)	119	void gdt_tss_setbase(struct descriptor *d, __address base)
123	{	120	{
124	struct tss_descriptor td = (struct tss_descriptor ) d;	121	struct tss_descriptor td = (struct tss_descriptor ) d;
125		122
126	td->base_0_15 = base & 0xffff;	123	td->base_0_15 = base & 0xffff;
127	td->base_16_23 = ((base) >> 16) & 0xff;	124	td->base_16_23 = ((base) >> 16) & 0xff;
128	td->base_24_31 = ((base) >> 24) & 0xff;	125	td->base_24_31 = ((base) >> 24) & 0xff;
129	td->base_32_63 = ((base) >> 32);	126	td->base_32_63 = ((base) >> 32);
130	}	127	}
131		128
132	void gdt_tss_setlimit(struct descriptor *d, __u32 limit)	129	void gdt_tss_setlimit(struct descriptor *d, __u32 limit)
133	{	130	{
134	struct tss_descriptor td = (struct tss_descriptor ) d;	131	struct tss_descriptor td = (struct tss_descriptor ) d;
135		132
136	td->limit_0_15 = limit & 0xffff;	133	td->limit_0_15 = limit & 0xffff;
137	td->limit_16_19 = (limit >> 16) & 0xf;	134	td->limit_16_19 = (limit >> 16) & 0xf;
138	}	135	}
139		136
140	void idt_setoffset(struct idescriptor *d, __address offset)	137	void idt_setoffset(struct idescriptor *d, __address offset)
141	{	138	{
142	/*	139	/*
143	* Offset is a linear address.	140	* Offset is a linear address.
144	*/	141	*/
145	d->offset_0_15 = offset & 0xffff;	142	d->offset_0_15 = offset & 0xffff;
146	d->offset_16_31 = offset >> 16 & 0xffff;	143	d->offset_16_31 = offset >> 16 & 0xffff;
147	d->offset_32_63 = offset >> 32;	144	d->offset_32_63 = offset >> 32;
148	}	145	}
149		146
150	void tss_initialize(struct tss *t)	147	void tss_initialize(struct tss *t)
151	{	148	{
152	memsetb((__address) t, sizeof(struct tss), 0);	149	memsetb((__address) t, sizeof(struct tss), 0);
153	}	150	}
154		151
155	/*	152	/*
156	* This function takes care of proper setup of IDT and IDTR.	153	* This function takes care of proper setup of IDT and IDTR.
157	*/	154	*/
158	void idt_init(void)	155	void idt_init(void)
159	{	156	{
160	struct idescriptor *d;	157	struct idescriptor *d;
161	int i;	158	int i;
162		159
163	for (i = 0; i < IDT_ITEMS; i++) {	160	for (i = 0; i < IDT_ITEMS; i++) {
164	d = &idt[i];	161	d = &idt[i];
165		162
166	d->unused = 0;	163	d->unused = 0;
167	d->selector = gdtselector(KTEXT_DES);	164	d->selector = gdtselector(KTEXT_DES);
168		165
169	d->present = 1;	166	d->present = 1;
170	d->type = AR_INTERRUPT; /* masking interrupt */	167	d->type = AR_INTERRUPT; /* masking interrupt */
171		168
172	if (i == VECTOR_SYSCALL) {	169	if (i == VECTOR_SYSCALL) {
173	/*	170	/*
174	* The syscall interrupt gate must be calleable from userland.	171	* The syscall interrupt gate must be calleable from userland.
175	*/	172	*/
176	d->dpl \|= PL_USER;	173	d->dpl \|= PL_USER;
177	}	174	}
178		175
179	idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);	176	idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
180	trap_register(i, null_interrupt);	177	trap_register(i, null_interrupt);
181	}	178	}
182	trap_register(13, gp_fault);	179	trap_register(13, gp_fault);
183	trap_register( 7, nm_fault);	180	trap_register( 7, nm_fault);
184	trap_register(12, ss_fault);	181	trap_register(12, ss_fault);
185	}	182	}
186		183
187		184
188	/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */	185	/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
189	static void clean_IOPL_NT_flags(void)	186	static void clean_IOPL_NT_flags(void)
190	{	187	{
191	asm	188	asm
192	(	189	(
193	"pushfq;"	190	"pushfq;"
194	"pop %%rax;"	191	"pop %%rax;"
195	"and $~(0x7000),%%rax;"	192	"and $~(0x7000),%%rax;"
196	"pushq %%rax;"	193	"pushq %%rax;"
197	"popfq;"	194	"popfq;"
198	:	195	:
199	:	196	:
200	:"%rax"	197	:"%rax"
201	);	198	);
202	}	199	}
203		200
204	/* Clean AM(18) flag in CR0 register */	201	/* Clean AM(18) flag in CR0 register */
205	static void clean_AM_flag(void)	202	static void clean_AM_flag(void)
206	{	203	{
207	asm	204	asm
208	(	205	(
209	"mov %%cr0,%%rax;"	206	"mov %%cr0,%%rax;"
210	"and $~(0x40000),%%rax;"	207	"and $~(0x40000),%%rax;"
211	"mov %%rax,%%cr0;"	208	"mov %%rax,%%cr0;"
212	:	209	:
213	:	210	:
214	:"%rax"	211	:"%rax"
215	);	212	);
216	}	213	}
217		214
218	void pm_init(void)	215	void pm_init(void)
219	{	216	{
220	struct descriptor gdt_p = (struct descriptor ) gdtr.base;	217	struct descriptor gdt_p = (struct descriptor ) gdtr.base;
221	struct tss_descriptor *tss_desc;	218	struct tss_descriptor *tss_desc;
222		219
223	/*	220	/*
224	* Each CPU has its private GDT and TSS.	221	* Each CPU has its private GDT and TSS.
225	* All CPUs share one IDT.	222	* All CPUs share one IDT.
226	*/	223	*/
227		224
228	if (config.cpu_active == 1) {	225	if (config.cpu_active == 1) {
229	idt_init();	226	idt_init();
230	/*	227	/*
231	* NOTE: bootstrap CPU has statically allocated TSS, because	228	* NOTE: bootstrap CPU has statically allocated TSS, because
232	* the heap hasn't been initialized so far.	229	* the heap hasn't been initialized so far.
233	*/	230	*/
234	tss_p = &tss;	231	tss_p = &tss;
235	}	232	}
236	else {	233	else {
237	tss_p = (struct tss *) malloc(sizeof(struct tss));	234	tss_p = (struct tss *) malloc(sizeof(struct tss));
238	if (!tss_p)	235	if (!tss_p)
239	panic("could not allocate TSS\n");	236	panic("could not allocate TSS\n");
240	}	237	}
241		238
242	tss_initialize(tss_p);	239	tss_initialize(tss_p);
243		240
244	tss_desc = (struct tss_descriptor *) (&gdt_p[TSS_DES]);	241	tss_desc = (struct tss_descriptor *) (&gdt_p[TSS_DES]);
245	tss_desc->present = 1;	242	tss_desc->present = 1;
246	tss_desc->type = AR_TSS;	243	tss_desc->type = AR_TSS;
247	tss_desc->dpl = PL_KERNEL;	244	tss_desc->dpl = PL_KERNEL;
248		245
249	gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);	246	gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
250	gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);	247	gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
251		248
252	__asm__("lgdt %0" : : "m"(gdtr));	249	__asm__("lgdt %0" : : "m"(gdtr));
253	__asm__("lidt %0" : : "m"(idtr));	250	__asm__("lidt %0" : : "m"(idtr));
254	/*	251	/*
255	* As of this moment, the current CPU has its own GDT pointing	252	* As of this moment, the current CPU has its own GDT pointing
256	* to its own TSS. We just need to load the TR register.	253	* to its own TSS. We just need to load the TR register.
257	*/	254	*/
258	__asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));	255	__asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));
259		256
260	clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */	257	clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */
261	clean_AM_flag(); /* Disable alignment check */	258	clean_AM_flag(); /* Disable alignment check */
262	}	259	}
263		260

Subversion Repositories HelenOS

(root)/SPARTAN/trunk/arch/amd64/src/pm.c – Rev 332 → 406