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Ignore whitespace Rev 1674 → Rev 1675

/kernel/trunk/arch/ia64/include/mm/tlb.h
79,6 → 79,7
extern void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr);
 
extern void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr);
extern void dtr_purge(__address page, count_t width);
 
extern void dtc_pte_copy(pte_t *t);
extern void itc_pte_copy(pte_t *t);
/kernel/trunk/arch/ia64/src/proc/scheduler.c
53,6 → 53,11
* Kernel stack of this thread is not mapped by DTR[TR_KERNEL].
* Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it.
*/
/* purge DTR[TR_STACK1] and DTR[TR_STACK2] */
dtr_purge((__address) THREAD->kstack, PAGE_WIDTH+1);
/* insert DTR[TR_STACK1] and DTR[TR_STACK2] */
dtlb_kernel_mapping_insert((__address) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK1);
dtlb_kernel_mapping_insert((__address) THREAD->kstack + PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, DTR_KSTACK2);
}
/kernel/trunk/arch/ia64/src/mm/tlb.c
189,7 → 189,6
}
}
 
 
/** Insert data into data translation cache.
*
* @param va Virtual page address.
341,9 → 340,8
 
/** Insert data into DTLB.
*
* @param va Virtual page address.
* @param asid Address space identifier.
* @param entry The rest of TLB entry as required by TLB insertion format.
* @param page Virtual page address including VRN bits.
* @param frame Physical frame address.
* @param dtr If true, insert into data translation register, use data translation cache otherwise.
* @param tr Translation register if dtr is true, ignored otherwise.
*/
369,6 → 367,19
dtc_mapping_insert(page, ASID_KERNEL, entry);
}
 
/** Purge kernel entries from DTR.
*
* Purge DTR entries used by the kernel.
*
* @param page Virtual page address including VRN bits.
* @param width Width of the purge in bits.
*/
void dtr_purge(__address page, count_t width)
{
__asm__ volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2));
}
 
 
/** Copy content of PTE into data translation cache.
*
* @param t PTE.