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Ignore whitespace Rev 786 → Rev 792

/kernel/trunk/arch/sparc64/include/types.h
44,7 → 44,7
 
typedef __u64 __native;
 
typedef __u64 pte_t;
typedef struct pte pte_t;
 
typedef __u8 asi_t;
 
/kernel/trunk/arch/sparc64/include/mm/page.h
41,16 → 41,6
 
#define SET_PTL0_ADDRESS_ARCH(x) /**< To be removed as situation permits. */
 
/** Implementation of page hash table interface. */
#define HT_WIDTH_ARCH 20 /* 1M */
#define HT_HASH_ARCH(page, asid) 0
#define HT_COMPARE_ARCH(page, asid, t) 0
#define HT_SLOT_EMPTY_ARCH(t) 1
#define HT_INVALIDATE_SLOT_ARCH(t)
#define HT_GET_NEXT_ARCH(t) 0
#define HT_SET_NEXT_ARCH(t, s)
#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags)
 
union page_address {
__address address;
struct {
/kernel/trunk/arch/sparc64/src/mm/frame.c
32,5 → 32,11
 
void frame_arch_init(void)
{
/*
* Workaround to prevent slab allocator from allocating fram 0,
* which is not, at that time, mapped.
*/
frame_region_not_free(0, FRAME_SIZE);
zone_create_in_region(0, config.memory_size & ~(FRAME_SIZE - 1));
}
/kernel/trunk/arch/ia64/include/types.h
47,6 → 47,6
 
typedef __u64 __native;
 
typedef union vhpt_entry pte_t;
typedef struct pte pte_t;
 
#endif
/kernel/trunk/arch/ia64/include/mm/page.h
45,16 → 45,6
 
#define SET_PTL0_ADDRESS_ARCH(x) /**< To be removed as situation permits. */
 
/** Implementation of page hash table interface. */
#define HT_WIDTH_ARCH 20 /* 1M */
#define HT_HASH_ARCH(page, asid) vhpt_hash((page), (asid))
#define HT_COMPARE_ARCH(page, asid, t) vhpt_compare((page), (asid), (t))
#define HT_SLOT_EMPTY_ARCH(t) ((t)->present.tag.tag_info.ti)
#define HT_INVALIDATE_SLOT_ARCH(t) (t)->present.tag.tag_info.ti = true
#define HT_GET_NEXT_ARCH(t) (t)->present.next
#define HT_SET_NEXT_ARCH(t, s) (t)->present.next = (s)
#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags) vhpt_set_record(t, page, asid, frame, flags)
 
#define PPN_SHIFT 12
 
#define VRN_SHIFT 61
63,8 → 53,8
#define REGION_REGISTERS 8
 
#define VHPT_WIDTH 20 /* 1M */
#define VHPT_SIZE (1<<VHPT_WIDTH)
#define VHPT_BASE page_ht /* Must be aligned to VHPT_SIZE */
#define VHPT_SIZE (1 << VHPT_WIDTH)
#define VHPT_BASE 0 /* Must be aligned to VHPT_SIZE */
 
#define PTA_BASE_SHIFT 15
 
115,7 → 105,7
union vhpt_tag tag;
/* Word 3 */
pte_t *next; /**< Collision chain next pointer. */
__u64 ig3 : 64;
} __attribute__ ((packed));
 
struct vhpt_entry_not_present {
133,8 → 123,7
union vhpt_tag tag;
/* Word 3 */
pte_t *next; /**< Collision chain next pointer. */
__u64 ig3 : 64;
} __attribute__ ((packed));
 
typedef union vhpt_entry {
141,7 → 130,7
struct vhpt_entry_present present;
struct vhpt_entry_not_present not_present;
__u64 word[4];
} vhpt_entry;
} vhpt_entry_t;
 
struct region_register_map {
unsigned ve : 1;
257,8 → 246,9
}
 
extern void page_arch_init(void);
extern pte_t *vhpt_hash(__address page, asid_t asid);
extern bool vhpt_compare(__address page, asid_t asid, pte_t *t);
extern void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags);
 
extern vhpt_entry_t *vhpt_hash(__address page, asid_t asid);
extern bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v);
extern void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags);
 
#endif
/kernel/trunk/arch/ia64/src/mm/page.c
42,7 → 42,7
#include <arch/barrier.h>
#include <memstr.h>
 
static void set_vhpt_environment(void);
static void set_environment(void);
 
/** Initialize ia64 virtual address translation subsystem. */
void page_arch_init(void)
49,11 → 49,11
{
page_operations = &page_ht_operations;
pk_disable();
set_vhpt_environment();
set_environment();
}
 
/** Initialize VHPT and region registers. */
void set_vhpt_environment(void)
void set_environment(void)
{
region_register rr;
pta_register pta;
87,13 → 87,6
}
 
/*
* Allocate VHPT and invalidate all its entries.
*/
page_ht = (pte_t *) frame_alloc(VHPT_WIDTH - FRAME_WIDTH, FRAME_KA);
memsetb((__address) page_ht, VHPT_SIZE, 0);
ht_invalidate_all();
/*
* Set up PTA register.
*/
pta.word = pta_read();
100,7 → 93,7
pta.map.ve = 0; /* disable VHPT walker */
pta.map.vf = 1; /* large entry format */
pta.map.size = VHPT_WIDTH;
pta.map.base = ((__address) page_ht) >> PTA_BASE_SHIFT;
pta.map.base = VHPT_BASE >> PTA_BASE_SHIFT;
pta_write(pta.word);
srlz_i();
srlz_d();
113,14 → 106,14
* @param page Address of virtual page including VRN bits.
* @param asid Address space identifier.
*
* @return Head of VHPT collision chain for page and asid.
* @return VHPT entry address.
*/
pte_t *vhpt_hash(__address page, asid_t asid)
vhpt_entry_t *vhpt_hash(__address page, asid_t asid)
{
region_register rr_save, rr;
index_t vrn;
rid_t rid;
pte_t *t;
vhpt_entry_t *v;
 
vrn = page >> VRN_SHIFT;
rid = ASID2RID(asid, vrn);
130,8 → 123,8
/*
* The RID is already in place, compute thash and return.
*/
t = (pte_t *) thash(page);
return t;
v = (vhpt_entry_t *) thash(page);
return v;
}
/*
142,12 → 135,12
rr.map.rid = rid;
rr_write(vrn, rr.word);
srlz_i();
t = (pte_t *) thash(page);
v = (vhpt_entry_t *) thash(page);
rr_write(vrn, rr_save.word);
srlz_i();
srlz_d();
 
return t;
return v;
}
 
/** Compare ASID and VPN against PTE.
159,7 → 152,7
*
* @return True if page and asid match the page and asid of t, false otherwise.
*/
bool vhpt_compare(__address page, asid_t asid, pte_t *t)
bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)
{
region_register rr_save, rr;
index_t vrn;
166,7 → 159,7
rid_t rid;
bool match;
 
ASSERT(t);
ASSERT(v);
 
vrn = page >> VRN_SHIFT;
rid = ASID2RID(asid, vrn);
176,7 → 169,7
/*
* The RID is already in place, compare ttag with t and return.
*/
return ttag(page) == t->present.tag.tag_word;
return ttag(page) == v->present.tag.tag_word;
}
/*
187,7 → 180,7
rr.map.rid = rid;
rr_write(vrn, rr.word);
srlz_i();
match = (ttag(page) == t->present.tag.tag_word);
match = (ttag(page) == v->present.tag.tag_word);
rr_write(vrn, rr_save.word);
srlz_i();
srlz_d();
203,7 → 196,7
* @param frame Physical address of the frame to wich page is mapped.
* @param flags Different flags for the mapping.
*/
void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags)
void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)
{
region_register rr_save, rr;
index_t vrn;
210,7 → 203,7
rid_t rid;
__u64 tag;
 
ASSERT(t);
ASSERT(v);
 
vrn = page >> VRN_SHIFT;
rid = ASID2RID(asid, vrn);
231,22 → 224,21
/*
* Clear the entry.
*/
t->word[0] = 0;
t->word[1] = 0;
t->word[2] = 0;
t->word[3] = 0;
v->word[0] = 0;
v->word[1] = 0;
v->word[2] = 0;
v->word[3] = 0;
t->present.p = true;
t->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
t->present.a = false; /* not accessed */
t->present.d = false; /* not dirty */
t->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
t->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
t->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
t->present.ppn = frame >> PPN_SHIFT;
t->present.ed = false; /* exception not deffered */
t->present.ps = PAGE_WIDTH;
t->present.key = 0;
t->present.tag.tag_word = tag;
t->present.next = NULL;
v->present.p = true;
v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
v->present.a = false; /* not accessed */
v->present.d = false; /* not dirty */
v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
v->present.ppn = frame >> PPN_SHIFT;
v->present.ed = false; /* exception not deffered */
v->present.ps = PAGE_WIDTH;
v->present.key = 0;
v->present.tag.tag_word = tag;
}