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Ignore whitespace Rev 1777 → Rev 1780

/kernel/trunk/arch/sparc64/include/interrupt.h
54,7 → 54,7
struct istate {
};
 
static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
{
/* TODO */
}
63,7 → 63,7
/* TODO */
return 0;
}
static inline __native istate_get_pc(istate_t *istate)
static inline unative_t istate_get_pc(istate_t *istate)
{
/* TODO */
return 0;
/kernel/trunk/arch/sparc64/include/byteorder.h
38,14 → 38,14
#include <arch/types.h>
#include <byteorder.h>
 
static inline __u64 __u64_le2host(__u64 n)
static inline uint64_t uint64_t_le2host(uint64_t n)
{
return __u64_byteorder_swap(n);
return uint64_t_byteorder_swap(n);
}
 
static inline __native __native_le2host(__native n)
static inline unative_t unative_t_le2host(unative_t n)
{
return __u64_byteorder_swap(n);
return uint64_t_byteorder_swap(n);
}
 
#endif
/kernel/trunk/arch/sparc64/include/types.h
37,27 → 37,27
 
#define NULL 0
 
typedef signed char __s8;
typedef signed short __s16;
typedef signed int __s32;
typedef signed long __s64;
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed int int32_t;
typedef signed long int64_t;
 
typedef unsigned char __u8;
typedef unsigned short __u16;
typedef unsigned int __u32;
typedef unsigned long __u64;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long uint64_t;
 
typedef __u64 __address;
typedef __u64 pfn_t;
typedef uint64_t uintptr_t;
typedef uint64_t pfn_t;
 
typedef __u64 ipl_t;
typedef uint64_t ipl_t;
 
typedef __u64 __native;
typedef __s64 __snative;
typedef uint64_t unative_t;
typedef int64_t native_t;
 
typedef struct pte pte_t;
 
typedef __u8 asi_t;
typedef uint8_t asi_t;
 
#endif
 
/kernel/trunk/arch/sparc64/include/memstr.h
37,10 → 37,10
 
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt))
 
extern void memsetw(__address dst, size_t cnt, __u16 x);
extern void memsetb(__address dst, size_t cnt, __u8 x);
extern void memsetw(uintptr_t dst, size_t cnt, uint16_t x);
extern void memsetb(uintptr_t dst, size_t cnt, uint8_t x);
 
extern int memcmp(__address src, __address dst, int cnt);
extern int memcmp(uintptr_t src, uintptr_t dst, int cnt);
 
#endif
 
/kernel/trunk/arch/sparc64/include/atomic.h
49,8 → 49,8
*/
static inline long atomic_add(atomic_t *val, int i)
{
__u64 a, b;
volatile __u64 x = (__u64) &val->count;
uint64_t a, b;
volatile uint64_t x = (uint64_t) &val->count;
 
__asm__ volatile (
"0:\n"
60,7 → 60,7
"cmp %1, %2\n"
"bne 0b\n" /* The operation failed and must be attempted again if a != b. */
"nop\n"
: "=m" (*((__u64 *)x)), "=r" (a), "=r" (b)
: "=m" (*((uint64_t *)x)), "=r" (a), "=r" (b)
: "r" (i)
);
 
/kernel/trunk/arch/sparc64/include/faddr.h
37,7 → 37,7
 
#include <arch/types.h>
 
#define FADDR(fptr) ((__address) (fptr))
#define FADDR(fptr) ((uintptr_t) (fptr))
 
#endif
 
/kernel/trunk/arch/sparc64/include/asm.h
44,9 → 44,9
*
* @return Value of PSTATE register.
*/
static inline __u64 pstate_read(void)
static inline uint64_t pstate_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
57,7 → 57,7
*
* @param v New value of PSTATE register.
*/
static inline void pstate_write(__u64 v)
static inline void pstate_write(uint64_t v)
{
__asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
}
66,9 → 66,9
*
* @return Value of TICK_comapre register.
*/
static inline __u64 tick_compare_read(void)
static inline uint64_t tick_compare_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
79,7 → 79,7
*
* @param v New value of TICK_comapre register.
*/
static inline void tick_compare_write(__u64 v)
static inline void tick_compare_write(uint64_t v)
{
__asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
}
88,9 → 88,9
*
* @return Value of TICK register.
*/
static inline __u64 tick_read(void)
static inline uint64_t tick_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
101,7 → 101,7
*
* @param v New value of TICK register.
*/
static inline void tick_write(__u64 v)
static inline void tick_write(uint64_t v)
{
__asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
}
110,9 → 110,9
*
* @return Value of SOFTINT register.
*/
static inline __u64 softint_read(void)
static inline uint64_t softint_read(void)
{
__u64 v;
uint64_t v;
 
__asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
 
123,7 → 123,7
*
* @param v New value of SOFTINT register.
*/
static inline void softint_write(__u64 v)
static inline void softint_write(uint64_t v)
{
__asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
}
134,7 → 134,7
*
* @param v New value of CLEAR_SOFTINT register.
*/
static inline void clear_softint_write(__u64 v)
static inline void clear_softint_write(uint64_t v)
{
__asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
}
148,7 → 148,7
*/
static inline ipl_t interrupts_enable(void) {
pstate_reg_t pstate;
__u64 value;
uint64_t value;
value = pstate_read();
pstate.value = value;
167,7 → 167,7
*/
static inline ipl_t interrupts_disable(void) {
pstate_reg_t pstate;
__u64 value;
uint64_t value;
value = pstate_read();
pstate.value = value;
207,9 → 207,9
* The stack is assumed to be STACK_SIZE bytes long.
* The stack must start on page boundary.
*/
static inline __address get_stack_base(void)
static inline uintptr_t get_stack_base(void)
{
__address v;
uintptr_t v;
__asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
220,9 → 220,9
*
* @return Value of VER register.
*/
static inline __u64 ver_read(void)
static inline uint64_t ver_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
233,9 → 233,9
*
* @return Current value in TBA.
*/
static inline __u64 tba_read(void)
static inline uint64_t tba_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
246,9 → 246,9
*
* @return Current value in TPC.
*/
static inline __u64 tpc_read(void)
static inline uint64_t tpc_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
259,9 → 259,9
*
* @return Current value in TL.
*/
static inline __u64 tl_read(void)
static inline uint64_t tl_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));
272,12 → 272,12
*
* @param v New value of TBA.
*/
static inline void tba_write(__u64 v)
static inline void tba_write(uint64_t v)
{
__asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
 
/** Load __u64 from alternate space.
/** Load uint64_t from alternate space.
*
* @param asi ASI determining the alternate space.
* @param va Virtual address within the ASI.
284,9 → 284,9
*
* @return Value read from the virtual address in the specified address space.
*/
static inline __u64 asi_u64_read(asi_t asi, __address va)
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
{
__u64 v;
uint64_t v;
__asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
293,13 → 293,13
return v;
}
 
/** Store __u64 to alternate space.
/** Store uint64_t to alternate space.
*
* @param asi ASI determining the alternate space.
* @param va Virtual address within the ASI.
* @param v Value to be written.
*/
static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
{
__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory");
}
308,7 → 308,7
 
void cpu_halt(void);
void cpu_sleep(void);
void asm_delay_loop(__u32 t);
void asm_delay_loop(uint32_t t);
 
#endif
 
/kernel/trunk/arch/sparc64/include/trap/trap_table.h
47,7 → 47,7
 
#ifndef __ASM__
struct trap_table_entry {
__u8 octets[TRAP_TABLE_ENTRY_SIZE];
uint8_t octets[TRAP_TABLE_ENTRY_SIZE];
} __attribute__ ((packed));
 
typedef struct trap_table_entry trap_table_entry_t;
/kernel/trunk/arch/sparc64/include/trap/trap.h
42,7 → 42,7
static inline void trap_switch_trap_table(void)
{
/* Point TBA to kernel copy of OFW's trap table. */
tba_write((__u64) trap_table);
tba_write((uint64_t) trap_table);
}
 
extern void trap_init(void);
/kernel/trunk/arch/sparc64/include/mm/frame.h
44,10 → 44,10
#include <arch/types.h>
 
union frame_address {
__address address;
uintptr_t address;
struct {
unsigned : 23;
__u64 pfn : 28; /**< Physical Frame Number. */
uint64_t pfn : 28; /**< Physical Frame Number. */
unsigned offset : 13; /**< Offset. */
} __attribute__ ((packed));
};
/kernel/trunk/arch/sparc64/include/mm/page.h
46,13 → 46,13
#include <arch/types.h>
#include <genarch/mm/page_ht.h>
 
#define KA2PA(x) ((__address) (x))
#define PA2KA(x) ((__address) (x))
#define KA2PA(x) ((uintptr_t) (x))
#define PA2KA(x) ((uintptr_t) (x))
 
union page_address {
__address address;
uintptr_t address;
struct {
__u64 vpn : 51; /**< Virtual Page Number. */
uint64_t vpn : 51; /**< Virtual Page Number. */
unsigned offset : 13; /**< Offset. */
} __attribute__ ((packed));
};
/kernel/trunk/arch/sparc64/include/mm/tte.h
39,13 → 39,13
 
/** Translation Table Entry - Tag. */
union tte_tag {
__u64 value;
uint64_t value;
struct {
unsigned g : 1; /**< Global. */
unsigned : 2; /**< Reserved. */
unsigned context : 13; /**< Context identifier. */
unsigned : 6; /**< Reserved. */
__u64 va_tag : 42; /**< Virtual Address Tag, bits 63:22. */
uint64_t va_tag : 42; /**< Virtual Address Tag, bits 63:22. */
} __attribute__ ((packed));
};
 
53,7 → 53,7
 
/** Translation Table Entry - Data. */
union tte_data {
__u64 value;
uint64_t value;
struct {
unsigned v : 1; /**< Valid. */
unsigned size : 2; /**< Page size of this entry. */
/kernel/trunk/arch/sparc64/include/mm/mmu.h
82,7 → 82,7
 
/** LSU Control Register. */
union lsu_cr_reg {
__u64 value;
uint64_t value;
struct {
unsigned : 23;
unsigned pm : 8;
/kernel/trunk/arch/sparc64/include/mm/asid.h
40,7 → 40,7
/*
* On SPARC, Context means the same thing as ASID trough out the kernel.
*/
typedef __u16 asid_t;
typedef uint16_t asid_t;
 
#define ASID_MAX_ARCH 8191 /* 2^13 - 1 */
 
/kernel/trunk/arch/sparc64/include/mm/tlb.h
56,7 → 56,7
#define KERNEL_PAGE_WIDTH 22 /* 4M */
 
union tlb_context_reg {
__u64 v;
uint64_t v;
struct {
unsigned long : 51;
unsigned context : 13; /**< Context/ASID. */
69,9 → 69,9
 
/** I-/D-TLB Data Access Address in Alternate Space. */
union tlb_data_access_addr {
__u64 value;
uint64_t value;
struct {
__u64 : 55;
uint64_t : 55;
unsigned tlb_entry : 6;
unsigned : 3;
} __attribute__ ((packed));
81,9 → 81,9
 
/** I-/D-TLB Tag Read Register. */
union tlb_tag_read_reg {
__u64 value;
uint64_t value;
struct {
__u64 vpn : 51; /**< Virtual Address bits 63:13. */
uint64_t vpn : 51; /**< Virtual Address bits 63:13. */
unsigned context : 13; /**< Context identifier. */
} __attribute__ ((packed));
};
101,9 → 101,9
 
/** TLB Demap Operation Address. */
union tlb_demap_addr {
__u64 value;
uint64_t value;
struct {
__u64 vpn: 51; /**< Virtual Address bits 63:13. */
uint64_t vpn: 51; /**< Virtual Address bits 63:13. */
unsigned : 6; /**< Ignored. */
unsigned type : 1; /**< The type of demap operation. */
unsigned context : 2; /**< Context register selection. */
114,7 → 114,7
 
/** TLB Synchronous Fault Status Register. */
union tlb_sfsr_reg {
__u64 value;
uint64_t value;
struct {
unsigned long : 39; /**< Implementation dependent. */
unsigned nf : 1; /**< Nonfaulting load. */
136,7 → 136,7
*
* @return Current value of Primary Context Register.
*/
static inline __u64 mmu_primary_context_read(void)
static inline uint64_t mmu_primary_context_read(void)
{
return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
}
145,7 → 145,7
*
* @param v New value of Primary Context Register.
*/
static inline void mmu_primary_context_write(__u64 v)
static inline void mmu_primary_context_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
flush();
155,7 → 155,7
*
* @return Current value of Secondary Context Register.
*/
static inline __u64 mmu_secondary_context_read(void)
static inline uint64_t mmu_secondary_context_read(void)
{
return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
}
164,7 → 164,7
*
* @param v New value of Primary Context Register.
*/
static inline void mmu_secondary_context_write(__u64 v)
static inline void mmu_secondary_context_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
flush();
176,7 → 176,7
*
* @return Current value of specified IMMU TLB Data Access Register.
*/
static inline __u64 itlb_data_access_read(index_t entry)
static inline uint64_t itlb_data_access_read(index_t entry)
{
tlb_data_access_addr_t reg;
190,7 → 190,7
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void itlb_data_access_write(index_t entry, __u64 value)
static inline void itlb_data_access_write(index_t entry, uint64_t value)
{
tlb_data_access_addr_t reg;
206,7 → 206,7
*
* @return Current value of specified DMMU TLB Data Access Register.
*/
static inline __u64 dtlb_data_access_read(index_t entry)
static inline uint64_t dtlb_data_access_read(index_t entry)
{
tlb_data_access_addr_t reg;
220,7 → 220,7
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void dtlb_data_access_write(index_t entry, __u64 value)
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
{
tlb_data_access_addr_t reg;
236,7 → 236,7
*
* @return Current value of specified IMMU TLB Tag Read Register.
*/
static inline __u64 itlb_tag_read_read(index_t entry)
static inline uint64_t itlb_tag_read_read(index_t entry)
{
tlb_tag_read_addr_t tag;
 
251,7 → 251,7
*
* @return Current value of specified DMMU TLB Tag Read Register.
*/
static inline __u64 dtlb_tag_read_read(index_t entry)
static inline uint64_t dtlb_tag_read_read(index_t entry)
{
tlb_tag_read_addr_t tag;
 
264,7 → 264,7
*
* @param v Value to be written.
*/
static inline void itlb_tag_access_write(__u64 v)
static inline void itlb_tag_access_write(uint64_t v)
{
asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
flush();
274,7 → 274,7
*
* @return Current value of IMMU TLB Tag Access Register.
*/
static inline __u64 itlb_tag_access_read(void)
static inline uint64_t itlb_tag_access_read(void)
{
return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
}
283,7 → 283,7
*
* @param v Value to be written.
*/
static inline void dtlb_tag_access_write(__u64 v)
static inline void dtlb_tag_access_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
flush();
293,7 → 293,7
*
* @return Current value of DMMU TLB Tag Access Register.
*/
static inline __u64 dtlb_tag_access_read(void)
static inline uint64_t dtlb_tag_access_read(void)
{
return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
}
303,7 → 303,7
*
* @param v Value to be written.
*/
static inline void itlb_data_in_write(__u64 v)
static inline void itlb_data_in_write(uint64_t v)
{
asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
flush();
313,7 → 313,7
*
* @param v Value to be written.
*/
static inline void dtlb_data_in_write(__u64 v)
static inline void dtlb_data_in_write(uint64_t v)
{
asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
flush();
323,7 → 323,7
*
* @return Current content of I-SFSR register.
*/
static inline __u64 itlb_sfsr_read(void)
static inline uint64_t itlb_sfsr_read(void)
{
return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
}
332,7 → 332,7
*
* @param v New value of I-SFSR register.
*/
static inline void itlb_sfsr_write(__u64 v)
static inline void itlb_sfsr_write(uint64_t v)
{
asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
flush();
342,7 → 342,7
*
* @return Current content of D-SFSR register.
*/
static inline __u64 dtlb_sfsr_read(void)
static inline uint64_t dtlb_sfsr_read(void)
{
return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
}
351,7 → 351,7
*
* @param v New value of D-SFSR register.
*/
static inline void dtlb_sfsr_write(__u64 v)
static inline void dtlb_sfsr_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
flush();
361,7 → 361,7
*
* @return Current content of D-SFAR register.
*/
static inline __u64 dtlb_sfar_read(void)
static inline uint64_t dtlb_sfar_read(void)
{
return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
}
372,7 → 372,7
* @param context_encoding Specifies which Context register has Context ID for demap.
* @param page Address which is on the page to be demapped.
*/
static inline void itlb_demap(int type, int context_encoding, __address page)
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
{
tlb_demap_addr_t da;
page_address_t pg;
394,7 → 394,7
* @param context_encoding Specifies which Context register has Context ID for demap.
* @param page Address which is on the page to be demapped.
*/
static inline void dtlb_demap(int type, int context_encoding, __address page)
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
{
tlb_demap_addr_t da;
page_address_t pg;
414,7 → 414,7
extern void fast_data_access_mmu_miss(void);
extern void fast_data_access_protection(void);
 
extern void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable);
extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
 
#endif
 
/kernel/trunk/arch/sparc64/include/context.h
54,8 → 54,8
#endif
 
#define context_set(c, _pc, stack, size) \
(c)->pc = ((__address) _pc) - 8; \
(c)->sp = ((__address) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - (STACK_BIAS + SP_DELTA); \
(c)->pc = ((uintptr_t) _pc) - 8; \
(c)->sp = ((uintptr_t) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - (STACK_BIAS + SP_DELTA); \
(c)->fp = -STACK_BIAS; \
(c)->cleanwin = 0
65,26 → 65,26
* function calls.
*/
struct context {
__address sp; /* %o6 */
__address pc; /* %o7 */
__u64 i0;
__u64 i1;
__u64 i2;
__u64 i3;
__u64 i4;
__u64 i5;
__address fp; /* %i6 */
__address i7;
__u64 l0;
__u64 l1;
__u64 l2;
__u64 l3;
__u64 l4;
__u64 l5;
__u64 l6;
__u64 l7;
uintptr_t sp; /* %o6 */
uintptr_t pc; /* %o7 */
uint64_t i0;
uint64_t i1;
uint64_t i2;
uint64_t i3;
uint64_t i4;
uint64_t i5;
uintptr_t fp; /* %i6 */
uintptr_t i7;
uint64_t l0;
uint64_t l1;
uint64_t l2;
uint64_t l3;
uint64_t l4;
uint64_t l5;
uint64_t l6;
uint64_t l7;
ipl_t ipl;
__u64 cleanwin;
uint64_t cleanwin;
};
 
#endif
/kernel/trunk/arch/sparc64/include/register.h
39,13 → 39,13
 
/** Version Register. */
union ver_reg {
__u64 value;
uint64_t value;
struct {
__u16 manuf; /**< Manufacturer code. */
__u16 impl; /**< Implementation code. */
__u8 mask; /**< Mask set revision. */
uint16_t manuf; /**< Manufacturer code. */
uint16_t impl; /**< Implementation code. */
uint8_t mask; /**< Mask set revision. */
unsigned : 8;
__u8 maxtl;
uint8_t maxtl;
unsigned : 3;
unsigned maxwin : 5;
} __attribute__ ((packed));
54,9 → 54,9
 
/** Processor State Register. */
union pstate_reg {
__u64 value;
uint64_t value;
struct {
__u64 : 52;
uint64_t : 52;
unsigned ig : 1; /**< Interrupt Globals. */
unsigned mg : 1; /**< MMU Globals. */
unsigned cle : 1; /**< Current Little Endian. */
74,10 → 74,10
 
/** TICK Register. */
union tick_reg {
__u64 value;
uint64_t value;
struct {
unsigned npt : 1; /**< Non-privileged Trap enable. */
__u64 counter : 63; /**< Elapsed CPU clck cycle counter. */
uint64_t counter : 63; /**< Elapsed CPU clck cycle counter. */
} __attribute__ ((packed));
};
typedef union tick_reg tick_reg_t;
84,10 → 84,10
 
/** TICK_compare Register. */
union tick_compare_reg {
__u64 value;
uint64_t value;
struct {
unsigned int_dis : 1; /**< TICK_INT interrupt disabled flag. */
__u64 tick_cmpr : 63; /**< Compare value for TICK interrupts. */
uint64_t tick_cmpr : 63; /**< Compare value for TICK interrupts. */
} __attribute__ ((packed));
};
typedef union tick_compare_reg tick_compare_reg_t;
94,9 → 94,9
 
/** SOFTINT Register. */
union softint_reg {
__u64 value;
uint64_t value;
struct {
__u64 : 47;
uint64_t : 47;
unsigned stick_int : 1;
unsigned int_level : 15;
unsigned tick_int : 1;
/kernel/trunk/arch/sparc64/include/drivers/i8042.h
45,24 → 45,24
 
#define LAST_REG DATA_REG
 
extern volatile __u8 *kbd_virt_address;
extern volatile uint8_t *kbd_virt_address;
 
static inline void i8042_data_write(__u8 data)
static inline void i8042_data_write(uint8_t data)
{
kbd_virt_address[DATA_REG] = data;
}
 
static inline __u8 i8042_data_read(void)
static inline uint8_t i8042_data_read(void)
{
return kbd_virt_address[DATA_REG];
}
 
static inline __u8 i8042_status_read(void)
static inline uint8_t i8042_status_read(void)
{
return kbd_virt_address[STATUS_REG];
}
 
static inline void i8042_command_write(__u8 command)
static inline void i8042_command_write(uint8_t command)
{
kbd_virt_address[COMMAND_REG] = command;
}