| 30,6 → 30,7 |
|---|
| #define __sparc64_TLB_H__ |
| |
| #include <arch/mm/tte.h> |
| #include <arch/mm/page.h> |
| #include <arch/asm.h> |
| #include <arch/barrier.h> |
| #include <arch/types.h> |
| 93,7 → 94,7 |
|---|
| union tlb_tag_read_reg { |
| __u64 value; |
| struct { |
| __u64 va : 51; /**< Virtual Address. */ |
| __u64 vpn : 51; /**< Virtual Address bits 63:13. */ |
| unsigned context : 13; /**< Context identifier. */ |
| } __attribute__ ((packed)); |
| }; |
| 100,6 → 101,28 |
|---|
| typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
| typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
| |
| /** TLB Demap Operation types. */ |
| #define TLB_DEMAP_PAGE 0 |
| #define TLB_DEMAP_CONTEXT 1 |
| |
| /** TLB Demap Operation Context register encodings. */ |
| #define TLB_DEMAP_PRIMARY 0 |
| #define TLB_DEMAP_SECONDARY 1 |
| #define TLB_DEMAP_NUCLEUS 2 |
| |
| /** TLB Demap Operation Address. */ |
| union tlb_demap_addr { |
| __u64 value; |
| struct { |
| __u64 vpn: 51; /**< Virtual Address bits 63:13. */ |
| unsigned : 6; /**< Ignored. */ |
| unsigned type : 1; /**< The type of demap operation. */ |
| unsigned context : 2; /**< Context register selection. */ |
| unsigned : 4; /**< Zero. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tlb_demap_addr tlb_demap_addr_t; |
| |
| /** Read IMMU TLB Data Access Register. |
| * |
| * @param entry TLB Entry index. |
| 115,6 → 138,21 |
|---|
| return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
| } |
| |
| /** Write IMMU TLB Data Access Register. |
| * |
| * @param entry TLB Entry index. |
| * @param value Value to be written. |
| */ |
| static inline __u64 itlb_data_access_write(index_t entry, __u64 value) |
| { |
| tlb_data_access_addr_t reg; |
| |
| reg.value = 0; |
| reg.tlb_entry = entry; |
| asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
| flush(); |
| } |
| |
| /** Read DMMU TLB Data Access Register. |
| * |
| * @param entry TLB Entry index. |
| 130,6 → 168,21 |
|---|
| return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
| } |
| |
| /** Write DMMU TLB Data Access Register. |
| * |
| * @param entry TLB Entry index. |
| * @param value Value to be written. |
| */ |
| static inline __u64 dtlb_data_access_write(index_t entry, __u64 value) |
| { |
| tlb_data_access_addr_t reg; |
| |
| reg.value = 0; |
| reg.tlb_entry = entry; |
| asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
| flush(); |
| } |
| |
| /** Read IMMU TLB Tag Read Register. |
| * |
| * @param entry TLB Entry index. |
| 200,4 → 253,48 |
|---|
| flush(); |
| } |
| |
| /** Perform IMMU TLB Demap Operation. |
| * |
| * @param type Selects between context and page demap. |
| * @param context_encoding Specifies which Context register has Context ID for demap. |
| * @param page Address which is on the page to be demapped. |
| */ |
| static inline void itlb_demap(int type, int context_encoding, __address page) |
| { |
| tlb_demap_addr_t da; |
| page_address_t pg; |
| |
| da.value = 0; |
| pg.address = page; |
| |
| da.type = type; |
| da.context = context_encoding; |
| da.vpn = pg.vpn; |
| |
| asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
| flush(); |
| } |
| |
| /** Perform DMMU TLB Demap Operation. |
| * |
| * @param type Selects between context and page demap. |
| * @param context_encoding Specifies which Context register has Context ID for demap. |
| * @param page Address which is on the page to be demapped. |
| */ |
| static inline void dtlb_demap(int type, int context_encoding, __address page) |
| { |
| tlb_demap_addr_t da; |
| page_address_t pg; |
| |
| da.value = 0; |
| pg.address = page; |
| |
| da.type = type; |
| da.context = context_encoding; |
| da.vpn = pg.vpn; |
| |
| asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
| flush(); |
| } |
| |
| #endif |