| /kernel/trunk/arch/sparc64/include/console.h |
|---|
| 29,7 → 29,6 |
| #ifndef __sparc64_CONSOLE_H__ |
| #define __sparc64_CONSOLE_H__ |
| extern void kofwinput(void *arg); |
| extern void ofw_sparc64_console_init(void); |
| extern void fb_sparc64_console_init(void); |
| #endif |
| /kernel/trunk/arch/sparc64/include/asm.h |
|---|
| 249,6 → 249,18 |
| return v; |
| } |
| /** Read Trap Level register. |
| * |
| * @return Current value in TL. |
| */ |
| static inline __u64 tl_read(void) |
| { |
| __u64 v; |
| __asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
| return v; |
| } |
| /** Write Trap Base Address register. |
| * |
| /kernel/trunk/arch/sparc64/include/trap/exception.h |
|---|
| 30,11 → 30,13 |
| #define __sparc64_EXCEPTION_H__ |
| #define TT_INSTRUCTION_ACCESS_EXCEPTION 0x08 |
| #define TT_ILLEGAL_INSTRUCTION 0x10 |
| #define TT_MEM_ADDRESS_NOT_ALIGNED 0x34 |
| #ifndef __ASM__ |
| extern void do_instruction_access_exc(void); |
| extern void do_mem_address_not_aligned(void); |
| extern void do_illegal_instruction(void); |
| #endif /* !__ASM__ */ |
| #endif |
| /kernel/trunk/arch/sparc64/include/trap/mmu.h |
|---|
| 33,6 → 33,8 |
| #ifndef __sparc64_MMU_TRAP_H__ |
| #define __sparc64_MMU_TRAP_H__ |
| #include <arch/stack.h> |
| #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 |
| #define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 |
| #define TT_FAST_DATA_ACCESS_PROTECTION 0x6c |
| 41,20 → 43,26 |
| #ifdef __ASM__ |
| .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER |
| save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
| call fast_instruction_access_mmu_miss |
| nop |
| restore |
| retry |
| .endm |
| .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER |
| save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
| call fast_data_access_mmu_miss |
| nop |
| restore |
| retry |
| .endm |
| .macro FAST_DATA_ACCESS_PROTECTION_HANDLER |
| save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
| call fast_data_access_protection |
| nop |
| restore |
| retry |
| .endm |
| #endif /* __ASM__ */ |
| /kernel/trunk/arch/sparc64/include/trap/trap.h |
|---|
| 40,6 → 40,5 |
| } |
| extern void trap_init(void); |
| extern void trap_install_handler(index_t tt, size_t len, bool tlnonz); |
| #endif |
| /kernel/trunk/arch/sparc64/include/barrier.h |
|---|
| 47,7 → 47,12 |
| * As such, it may trap if the address is not found in DTLB. |
| * However, JPS1 implementations are free to ignore the trap. |
| */ |
| __asm__ volatile ("flush %sp\n"); |
| /* |
| * %i7 should provide address that is always mapped in DTLB |
| * as it is a pointer to kernel code. |
| */ |
| __asm__ volatile ("flush %i7\n"); |
| } |
| /** Memory Barrier instruction. */ |