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Ignore whitespace Rev 568 → Rev 569

/kernel/trunk/arch/sparc64/include/types.h
46,4 → 46,6
 
typedef __u64 pte_t;
 
typedef __u8 asi_t;
 
#endif
/kernel/trunk/arch/sparc64/include/asm.h
107,7 → 107,34
__asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
 
/** Load __u64 from alternate space.
*
* @param asi ASI determining the alternate space.
* @param va Virtual address within the ASI.
*
* @return Value read from the virtual address in the specified address space.
*/
static inline __u64 asi_u64_read(asi_t asi, __address va)
{
__u64 v;
__asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
return v;
}
 
/** Store __u64 to alternate space.
*
* @param asi ASI determining the alternate space.
* @param va Virtual address within the ASI.
* @param v Value to be written.
*/
static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
{
__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi));
}
 
 
void cpu_halt(void);
void cpu_sleep(void);
void asm_delay_loop(__u32 t);
/kernel/trunk/arch/sparc64/include/mm/tlb.h
30,7 → 30,13
#define __sparc64_TLB_H__
 
#include <arch/mm/tte.h>
#include <arch/asm.h>
#include <arch/types.h>
#include <typedefs.h>
 
#define ITLB_ENTRY_COUNT 64
#define DTLB_ENTRY_COUNT 64
 
/** I-MMU ASIs. */
#define ASI_IMMU 0x50
#define ASI_IMMU_TSB_8KB_PTR_REG 0x51
70,6 → 76,86
/** I-/D-TLB Data In/Access Register type. */
typedef tte_data_t tlb_data_t;
 
#define tlb_init_arch()
/** I-/D-TLB Data Access Address in Alternate Space. */
union tlb_data_access_addr {
__u64 value;
struct {
__u64 : 55;
unsigned tlb_entry : 6;
unsigned : 3;
} __attribute__ ((packed));
};
typedef union tlb_data_access_addr tlb_data_access_addr_t;
typedef union tlb_data_access_addr tlb_tag_read_addr_t;
 
/** I-/D-TLB Tag Read Register. */
union tlb_tag_read_reg {
__u64 value;
struct {
__u64 va : 51; /**< Virtual Address. */
unsigned context : 13; /**< Context identifier. */
} __attribute__ ((packed));
};
typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
 
/** Read IMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Data Access Register.
*/
static inline __u64 itlb_data_access_read(index_t entry)
{
tlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Read DMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Data Access Register.
*/
static inline __u64 dtlb_data_access_read(index_t entry)
{
tlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Read IMMU TLB Tag Read Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Tag Read Register.
*/
static inline __u64 itlb_tag_read(index_t entry)
{
tlb_tag_read_addr_t tag;
 
tag.value = 0;
tag.tlb_entry = entry;
return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Tag Read Register.
*/
static inline __u64 dtlb_tag_read(index_t entry)
{
tlb_tag_read_addr_t tag;
 
tag.value = 0;
tag.tlb_entry = entry;
return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#endif
/kernel/trunk/arch/sparc64/include/barrier.h
39,4 → 39,6
#define read_barrier()
#define write_barrier()
 
#define flush() __asm__ volatile ("flush\n" ::: "memory")
 
#endif