| 39,11 → 39,12 |
|---|
| * |
| * @return Old interrupt priority level. |
| */ |
| static inline ipl_t interrupts_enable(void) { |
| static inline ipl_t interrupts_enable(void) |
| { |
| ipl_t v; |
| ipl_t tmp; |
| |
| __asm__ volatile ( |
| asm volatile ( |
| "mfmsr %0\n" |
| "mfmsr %1\n" |
| "ori %1, %1, 1 << 15\n" |
| 60,11 → 61,12 |
|---|
| * |
| * @return Old interrupt priority level. |
| */ |
| static inline ipl_t interrupts_disable(void) { |
| static inline ipl_t interrupts_disable(void) |
| { |
| ipl_t v; |
| ipl_t tmp; |
| |
| __asm__ volatile ( |
| asm volatile ( |
| "mfmsr %0\n" |
| "mfmsr %1\n" |
| "rlwinm %1, %1, 0, 17, 15\n" |
| 80,10 → 82,11 |
|---|
| * |
| * @param ipl Saved interrupt priority level. |
| */ |
| static inline void interrupts_restore(ipl_t ipl) { |
| static inline void interrupts_restore(ipl_t ipl) |
| { |
| ipl_t tmp; |
| |
| __asm__ volatile ( |
| asm volatile ( |
| "mfmsr %1\n" |
| "rlwimi %0, %1, 0, 17, 15\n" |
| "cmpw 0, %0, %1\n" |
| 92,6 → 95,7 |
|---|
| "0:\n" |
| : "=r" (ipl), "=r" (tmp) |
| : "0" (ipl) |
| : "cr0" |
| ); |
| } |
| |
| 101,9 → 105,11 |
|---|
| * |
| * @return Current interrupt priority level. |
| */ |
| static inline ipl_t interrupts_read(void) { |
| static inline ipl_t interrupts_read(void) |
| { |
| ipl_t v; |
| __asm__ volatile ( |
| |
| asm volatile ( |
| "mfmsr %0\n" |
| : "=r" (v) |
| ); |
| 120,8 → 126,11 |
|---|
| { |
| __address v; |
| |
| __asm__ volatile ("and %0, %%sp, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
| |
| asm volatile ( |
| "and %0, %%sp, %1\n" |
| : "=r" (v) |
| : "r" (~(STACK_SIZE - 1)) |
| ); |
| return v; |
| } |
| |
| 132,4 → 141,6 |
|---|
| void cpu_halt(void); |
| void asm_delay_loop(__u32 t); |
| |
| extern void userspace_asm(__address uspace_uarg, __address stack, __address entry); |
| |
| #endif |