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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /kernel/trunk/arch/mips32/src @ 1754

  → /kernel/trunk/arch/mips32/src/ @ 1769

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 1754 → Rev 1769

/kernel/trunk/arch/mips32/src/exception.c
48,23 → 48,26
#include <arch/debugger.h>
static char * exctable[] = {
"Interrupt","TLB Modified","TLB Invalid","TLB Invalid Store",
"Address Error - load/instr. fetch",
"Address Error - store",
"Bus Error - fetch instruction",
"Bus Error - data reference",
"Syscall",
"BreakPoint",
"Reserved Instruction",
"Coprocessor Unusable",
"Arithmetic Overflow",
"Trap",
"Virtual Coherency - instruction",
"Floating Point",
NULL, NULL, NULL, NULL, NULL, NULL, NULL,
"WatchHi/WatchLo", /* 23 */
NULL, NULL, NULL, NULL, NULL, NULL, NULL,
"Virtual Coherency - data",
"Interrupt",
"TLB Modified",
"TLB Invalid",
"TLB Invalid Store",
"Address Error - load/instr. fetch",
"Address Error - store",
"Bus Error - fetch instruction",
"Bus Error - data reference",
"Syscall",
"BreakPoint",
"Reserved Instruction",
"Coprocessor Unusable",
"Arithmetic Overflow",
"Trap",
"Virtual Coherency - instruction",
"Floating Point",
NULL, NULL, NULL, NULL, NULL, NULL, NULL,
"WatchHi/WatchLo", /* 23 */
NULL, NULL, NULL, NULL, NULL, NULL, NULL,
"Virtual Coherency - data",
};
static void print_regdump(istate_t *istate)
174,4 → 177,3
/** @}
*/

/kernel/trunk/arch/mips32/src/cache.c
26,7 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup mips32
/** @addtogroup mips32
* @{
*/
/** @file
33,13 → 33,15
*/
#include <arch/cache.h>
#include <arch/exception.h>
#include <typedefs.h>
#include <panic.h>
void cache_error(void)
void cache_error(istate_t *istate)
{
panic("cache_error exception\n");
panic("cache_error exception (epc=%p)\n", istate->epc);
}
/** @}
/** @}
*/

/kernel/trunk/arch/mips32/src/start.S
309,7 → 309,7
sw $sp,EOFFSET_SP($k0)
add $sp, $k0, 0
jal tlb_refill /* tlb_refill(register_space) */
jal tlb_refill
add $a0, $sp, 0
REGISTERS_LOAD $sp
324,7 → 324,7
add $sp, $k0, 0
jal cache_error
nop
add $a0, $sp, 0
REGISTERS_LOAD $sp