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Ignore whitespace Rev 1767 → Rev 1780

/kernel/trunk/arch/ia64/include/interrupt.h
88,38 → 88,38
__r128 f30;
__r128 f31;
__address ar_bsp;
__address ar_bspstore;
__address ar_bspstore_new;
__u64 ar_rnat;
__u64 ar_ifs;
__u64 ar_pfs;
__u64 ar_rsc;
__address cr_ifa;
uintptr_t ar_bsp;
uintptr_t ar_bspstore;
uintptr_t ar_bspstore_new;
uint64_t ar_rnat;
uint64_t ar_ifs;
uint64_t ar_pfs;
uint64_t ar_rsc;
uintptr_t cr_ifa;
cr_isr_t cr_isr;
__address cr_iipa;
uintptr_t cr_iipa;
psr_t cr_ipsr;
__address cr_iip;
__u64 pr;
__address sp;
uintptr_t cr_iip;
uint64_t pr;
uintptr_t sp;
/*
* The following variables are defined only for break_instruction handler.
*/
__u64 in0;
__u64 in1;
__u64 in2;
__u64 in3;
__u64 in4;
uint64_t in0;
uint64_t in1;
uint64_t in2;
uint64_t in3;
uint64_t in4;
};
 
static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
{
istate->cr_iip = retaddr;
istate->cr_ipsr.ri = 0; /* return to instruction slot #0 */
}
 
static inline __native istate_get_pc(istate_t *istate)
static inline unative_t istate_get_pc(istate_t *istate)
{
return istate->cr_iip;
}
131,13 → 131,13
 
extern void *ivt;
 
extern void general_exception(__u64 vector, istate_t *istate);
extern int break_instruction(__u64 vector, istate_t *istate);
extern void universal_handler(__u64 vector, istate_t *istate);
extern void nop_handler(__u64 vector, istate_t *istate);
extern void external_interrupt(__u64 vector, istate_t *istate);
extern void virtual_interrupt(__u64 irq, void *param);
extern void disabled_fp_register(__u64 vector, istate_t *istate);
extern void general_exception(uint64_t vector, istate_t *istate);
extern int break_instruction(uint64_t vector, istate_t *istate);
extern void universal_handler(uint64_t vector, istate_t *istate);
extern void nop_handler(uint64_t vector, istate_t *istate);
extern void external_interrupt(uint64_t vector, istate_t *istate);
extern void virtual_interrupt(uint64_t irq, void *param);
extern void disabled_fp_register(uint64_t vector, istate_t *istate);
 
 
 
/kernel/trunk/arch/ia64/include/byteorder.h
36,8 → 36,8
#define __ia64_BYTEORDER_H__
 
/* IA-64 is little-endian */
#define __native_le2host(n) (n)
#define __u64_le2host(n) (n)
#define unative_t_le2host(n) (n)
#define uint64_t_le2host(n) (n)
 
#endif
 
/kernel/trunk/arch/ia64/include/types.h
26,7 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup ia64
/** @addtogroup ia64
* @{
*/
/** @file
37,36 → 37,37
 
#define NULL 0
 
typedef signed char __s8;
typedef signed short int __s16;
typedef signed int __s32;
typedef signed long __s64;
typedef signed char int8_t;
typedef signed short int int16_t;
typedef signed int int32_t;
typedef signed long int64_t;
 
typedef unsigned char __u8;
typedef unsigned short __u16;
typedef unsigned int __u32;
typedef unsigned long __u64;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long uint64_t;
 
 
typedef unsigned char __r8; /*Reserve byte*/
typedef unsigned char __r8; /* Reserve byte */
typedef unsigned short __r16;
typedef unsigned int __r32;
typedef unsigned long __r64;
typedef struct __r128{__r64 lo;__r64 hi;} __r128;
typedef struct __r128 {
__r64 lo;
__r64 hi;
} __r128;
 
typedef uint64_t uintptr_t;
typedef uint64_t pfn_t;
 
typedef __u64 __address;
typedef __u64 pfn_t;
typedef uint64_t ipl_t;
 
typedef __u64 ipl_t;
typedef uint64_t unative_t;
typedef int64_t native_t;
 
typedef __u64 __native;
typedef __s64 __snative;
 
typedef struct pte pte_t;
 
#endif
 
/** @}
/** @}
*/
 
/kernel/trunk/arch/ia64/include/memstr.h
37,10 → 37,10
 
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt))
 
extern void memsetw(__address dst, size_t cnt, __u16 x);
extern void memsetb(__address dst, size_t cnt, __u8 x);
extern void memsetw(uintptr_t dst, size_t cnt, uint16_t x);
extern void memsetb(uintptr_t dst, size_t cnt, uint8_t x);
 
extern int memcmp(__address src, __address dst, int cnt);
extern int memcmp(uintptr_t src, uintptr_t dst, int cnt);
 
#endif
 
/kernel/trunk/arch/ia64/include/faddr.h
26,14 → 26,14
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup ia64
/** @addtogroup ia64
* @{
*/
/** @file
*/
 
#ifndef __ia64_FADDR_H__
#define __ia64_FADDR_H__
#ifndef KERN_ia64_FADDR_H_
#define KERN_ia64_FADDR_H_
 
#include <arch/types.h>
 
45,10 → 45,9
* @param f Function pointer.
*
*/
#define FADDR(f) (*((__address *)(f)));
#define FADDR(f) (*((uintptr_t *)(f)));
 
#endif
 
/** @}
/** @}
*/
 
/kernel/trunk/arch/ia64/include/asm.h
45,9 → 45,9
* The stack is assumed to be STACK_SIZE long.
* The stack must start on page boundary.
*/
static inline __address get_stack_base(void)
static inline uintptr_t get_stack_base(void)
{
__u64 v;
uint64_t v;
 
__asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
58,9 → 58,9
*
* @return PSR.
*/
static inline __u64 psr_read(void)
static inline uint64_t psr_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("mov %0 = psr\n" : "=r" (v));
71,9 → 71,9
*
* @return Return location of interruption vector table.
*/
static inline __u64 iva_read(void)
static inline uint64_t iva_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("mov %0 = cr.iva\n" : "=r" (v));
84,7 → 84,7
*
* @param v New location of interruption vector table.
*/
static inline void iva_write(__u64 v)
static inline void iva_write(uint64_t v)
{
__asm__ volatile ("mov cr.iva = %0\n" : : "r" (v));
}
94,9 → 94,9
*
* @return Highest priority, pending, unmasked external interrupt vector.
*/
static inline __u64 ivr_read(void)
static inline uint64_t ivr_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v));
107,7 → 107,7
*
* @param v New counter value.
*/
static inline void itc_write(__u64 v)
static inline void itc_write(uint64_t v)
{
__asm__ volatile ("mov ar.itc = %0\n" : : "r" (v));
}
116,9 → 116,9
*
* @return Current counter value.
*/
static inline __u64 itc_read(void)
static inline uint64_t itc_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v));
129,7 → 129,7
*
* @param v New match value.
*/
static inline void itm_write(__u64 v)
static inline void itm_write(uint64_t v)
{
__asm__ volatile ("mov cr.itm = %0\n" : : "r" (v));
}
138,9 → 138,9
*
* @return Match value.
*/
static inline __u64 itm_read(void)
static inline uint64_t itm_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("mov %0 = cr.itm\n" : "=r" (v));
151,9 → 151,9
*
* @return Current vector and mask bit.
*/
static inline __u64 itv_read(void)
static inline uint64_t itv_read(void)
{
__u64 v;
uint64_t v;
__asm__ volatile ("mov %0 = cr.itv\n" : "=r" (v));
164,7 → 164,7
*
* @param v New vector and mask bit.
*/
static inline void itv_write(__u64 v)
static inline void itv_write(uint64_t v)
{
__asm__ volatile ("mov cr.itv = %0\n" : : "r" (v));
}
173,7 → 173,7
*
* @param v This value is ignored.
*/
static inline void eoi_write(__u64 v)
static inline void eoi_write(uint64_t v)
{
__asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v));
}
182,9 → 182,9
*
* @return Current value of TPR.
*/
static inline __u64 tpr_read(void)
static inline uint64_t tpr_read(void)
{
__u64 v;
uint64_t v;
 
__asm__ volatile ("mov %0 = cr.tpr\n" : "=r" (v));
195,7 → 195,7
*
* @param v New value of TPR.
*/
static inline void tpr_write(__u64 v)
static inline void tpr_write(uint64_t v)
{
__asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v));
}
209,7 → 209,7
*/
static ipl_t interrupts_disable(void)
{
__u64 v;
uint64_t v;
__asm__ volatile (
"mov %0 = psr\n"
230,7 → 230,7
*/
static ipl_t interrupts_enable(void)
{
__u64 v;
uint64_t v;
__asm__ volatile (
"mov %0 = psr\n"
275,9 → 275,9
 
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(__u32 t);
extern void asm_delay_loop(uint32_t t);
 
extern void switch_to_userspace(__address entry, __address sp, __address bsp, __address uspace_uarg, __u64 ipsr, __u64 rsc);
extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc);
 
#endif
 
/kernel/trunk/arch/ia64/include/mm/page.h
27,7 → 27,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup ia64mm
/** @addtogroup ia64mm
* @{
*/
/** @file
61,8 → 61,8
 
#define REGION_REGISTERS 8
 
#define KA2PA(x) ((__address) (x-(VRN_KERNEL<<VRN_SHIFT)))
#define PA2KA(x) ((__address) (x+(VRN_KERNEL<<VRN_SHIFT)))
#define KA2PA(x) ((uintptr_t) (x-(VRN_KERNEL<<VRN_SHIFT)))
#define PA2KA(x) ((uintptr_t) (x+(VRN_KERNEL<<VRN_SHIFT)))
 
#define VHPT_WIDTH 20 /* 1M */
#define VHPT_SIZE (1 << VHPT_WIDTH)
126,7 → 126,7
union vhpt_tag tag;
/* Word 3 */
__u64 ig3 : 64;
uint64_t ig3 : 64;
} __attribute__ ((packed));
 
struct vhpt_entry_not_present {
144,13 → 144,13
union vhpt_tag tag;
/* Word 3 */
__u64 ig3 : 64;
uint64_t ig3 : 64;
} __attribute__ ((packed));
 
typedef union vhpt_entry {
struct vhpt_entry_present present;
struct vhpt_entry_not_present not_present;
__u64 word[4];
uint64_t word[4];
} vhpt_entry_t;
 
struct region_register_map {
177,7 → 177,7
 
typedef union pta_register {
struct pta_register_map map;
__u64 word;
uint64_t word;
} pta_register;
 
/** Return Translation Hashed Entry Address.
189,9 → 189,9
*
* @return Address of the head of VHPT collision chain.
*/
static inline __u64 thash(__u64 va)
static inline uint64_t thash(uint64_t va)
{
__u64 ret;
uint64_t ret;
 
__asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
 
207,9 → 207,9
*
* @return The unique tag for VPN and RID in the collision chain returned by thash().
*/
static inline __u64 ttag(__u64 va)
static inline uint64_t ttag(uint64_t va)
{
__u64 ret;
uint64_t ret;
 
__asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
 
222,9 → 222,9
*
* @return Current contents of rr[i].
*/
static inline __u64 rr_read(index_t i)
static inline uint64_t rr_read(index_t i)
{
__u64 ret;
uint64_t ret;
ASSERT(i < REGION_REGISTERS);
__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
return ret;
235,7 → 235,7
* @param i Region register index.
* @param v Value to be written to rr[i].
*/
static inline void rr_write(index_t i, __u64 v)
static inline void rr_write(index_t i, uint64_t v)
{
ASSERT(i < REGION_REGISTERS);
__asm__ volatile (
249,9 → 249,9
*
* @return Current value stored in PTA.
*/
static inline __u64 pta_read(void)
static inline uint64_t pta_read(void)
{
__u64 ret;
uint64_t ret;
__asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
262,7 → 262,7
*
* @param v New value to be stored in PTA.
*/
static inline void pta_write(__u64 v)
static inline void pta_write(uint64_t v)
{
__asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
}
269,9 → 269,9
 
extern void page_arch_init(void);
 
extern vhpt_entry_t *vhpt_hash(__address page, asid_t asid);
extern bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v);
extern void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags);
extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid);
extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v);
extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags);
 
#endif /* __ASM__ */
 
279,6 → 279,5
 
#endif
 
/** @}
/** @}
*/
 
/kernel/trunk/arch/ia64/include/mm/asid.h
39,8 → 39,8
 
#include <arch/types.h>
 
typedef __u16 asid_t;
typedef __u32 rid_t;
typedef uint16_t asid_t;
typedef uint32_t rid_t;
 
#endif /* __ASM__ */
 
/kernel/trunk/arch/ia64/include/mm/tlb.h
52,7 → 52,7
 
/** Portion of TLB insertion format data structure. */
union tlb_entry {
__u64 word[2];
uint64_t word[2];
struct {
/* Word 0 */
unsigned p : 1; /**< Present. */
76,27 → 76,27
} __attribute__ ((packed));
typedef union tlb_entry tlb_entry_t;
 
extern void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc);
extern void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry);
extern void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry);
extern void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc);
extern void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry);
extern void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry);
 
extern void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr);
extern void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr);
extern void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr);
extern void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr);
extern void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr);
extern void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr);
 
extern void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr);
extern void dtr_purge(__address page, count_t width);
extern void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr);
extern void dtr_purge(uintptr_t page, count_t width);
 
extern void dtc_pte_copy(pte_t *t);
extern void itc_pte_copy(pte_t *t);
 
extern void alternate_instruction_tlb_fault(__u64 vector, istate_t *istate);
extern void alternate_data_tlb_fault(__u64 vector, istate_t *istate);
extern void data_nested_tlb_fault(__u64 vector, istate_t *istate);
extern void data_dirty_bit_fault(__u64 vector, istate_t *istate);
extern void instruction_access_bit_fault(__u64 vector, istate_t *istate);
extern void data_access_bit_fault(__u64 vector, istate_t *istate);
extern void page_not_present(__u64 vector, istate_t *istate);
extern void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate);
extern void alternate_data_tlb_fault(uint64_t vector, istate_t *istate);
extern void data_nested_tlb_fault(uint64_t vector, istate_t *istate);
extern void data_dirty_bit_fault(uint64_t vector, istate_t *istate);
extern void instruction_access_bit_fault(uint64_t vector, istate_t *istate);
extern void data_access_bit_fault(uint64_t vector, istate_t *istate);
extern void page_not_present(uint64_t vector, istate_t *istate);
 
#endif
 
/kernel/trunk/arch/ia64/include/mm/vhpt.h
39,7 → 39,7
#include <arch/mm/tlb.h>
#include <arch/mm/page.h>
 
__address vhpt_set_up(void);
uintptr_t vhpt_set_up(void);
 
static inline vhpt_entry_t tlb_entry_t2vhpt_entry_t(tlb_entry_t tentry)
{
51,7 → 51,7
return ventry;
}
 
void vhpt_mapping_insert(__address va, asid_t asid, tlb_entry_t entry);
void vhpt_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry);
void vhpt_invalidate_all(void);
void vhpt_invalidate_asid(asid_t asid);
 
/kernel/trunk/arch/ia64/include/context.h
56,10 → 56,10
/* RSE stack starts at the bottom of memory stack. */
#define context_set(c, _pc, stack, size) \
do { \
(c)->pc = (__address) _pc; \
(c)->bsp = ((__address) stack) + ALIGN_UP((size), REGISTER_STACK_ALIGNMENT); \
(c)->pc = (uintptr_t) _pc; \
(c)->bsp = ((uintptr_t) stack) + ALIGN_UP((size), REGISTER_STACK_ALIGNMENT); \
(c)->ar_pfs &= PFM_MASK; \
(c)->sp = ((__address) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - SP_DELTA; \
(c)->sp = ((uintptr_t) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - SP_DELTA; \
} while (0);
 
/*
71,39 → 71,39
/*
* Application registers
*/
__u64 ar_pfs;
__u64 ar_unat_caller;
__u64 ar_unat_callee;
__u64 ar_rsc;
__address bsp; /* ar_bsp */
__u64 ar_rnat;
__u64 ar_lc;
uint64_t ar_pfs;
uint64_t ar_unat_caller;
uint64_t ar_unat_callee;
uint64_t ar_rsc;
uintptr_t bsp; /* ar_bsp */
uint64_t ar_rnat;
uint64_t ar_lc;
 
/*
* General registers
*/
__u64 r1;
__u64 r4;
__u64 r5;
__u64 r6;
__u64 r7;
__address sp; /* r12 */
__u64 r13;
uint64_t r1;
uint64_t r4;
uint64_t r5;
uint64_t r6;
uint64_t r7;
uintptr_t sp; /* r12 */
uint64_t r13;
/*
* Branch registers
*/
__address pc; /* b0 */
__u64 b1;
__u64 b2;
__u64 b3;
__u64 b4;
__u64 b5;
uintptr_t pc; /* b0 */
uint64_t b1;
uint64_t b2;
uint64_t b3;
uint64_t b4;
uint64_t b5;
 
/*
* Predicate registers
*/
__u64 pr;
uint64_t pr;
 
__r128 f2 __attribute__ ((aligned(16)));
__r128 f3;
/kernel/trunk/arch/ia64/include/register.h
136,7 → 136,7
 
/** Processor Status Register. */
union psr {
__u64 value;
uint64_t value;
struct {
unsigned : 1;
unsigned be : 1; /**< Big-Endian data accesses. */
179,7 → 179,7
 
/** Register Stack Configuration Register */
union rsc {
__u64 value;
uint64_t value;
struct {
unsigned mode : 2;
unsigned pl : 2; /**< Privilege Level. */
192,8 → 192,8
 
/** External Interrupt Vector Register */
union cr_ivr {
__u8 vector;
__u64 value;
uint8_t vector;
uint64_t value;
};
 
typedef union cr_ivr cr_ivr_t;
206,7 → 206,7
unsigned : 8;
unsigned mmi: 1; /**< Mask Maskable Interrupts. */
} __attribute__ ((packed));
__u64 value;
uint64_t value;
};
 
typedef union cr_tpr cr_tpr_t;
220,7 → 220,7
unsigned : 3;
unsigned m : 1; /**< Mask. */
} __attribute__ ((packed));
__u64 value;
uint64_t value;
};
 
typedef union cr_itv cr_itv_t;
234,9 → 234,9
unsigned ge_na : 4;
unsigned ge_code : 4;
} __attribute__ ((packed));
__u16 code;
uint16_t code;
};
__u8 vector;
uint8_t vector;
unsigned : 8;
unsigned x : 1; /**< Execute exception. */
unsigned w : 1; /**< Write exception. */
251,7 → 251,7
unsigned ed : 1; /**< Exception Deferral. */
unsigned : 20;
} __attribute__ ((packed));
__u64 value;
uint64_t value;
};
 
typedef union cr_isr cr_isr_t;
259,13 → 259,13
/** CPUID Register 3 */
union cpuid3 {
struct {
__u8 number;
__u8 revision;
__u8 model;
__u8 family;
__u8 archrev;
uint8_t number;
uint8_t revision;
uint8_t model;
uint8_t family;
uint8_t archrev;
} __attribute__ ((packed));
__u64 value;
uint64_t value;
};
 
typedef union cpuid3 cpuid3_t;
/kernel/trunk/arch/ia64/include/cpu.h
43,8 → 43,8
#define FAMILY_ITANIUM2 0x1f
 
struct cpu_arch {
__u64 cpuid0;
__u64 cpuid1;
uint64_t cpuid0;
uint64_t cpuid1;
cpuid3_t cpuid3;
};
 
54,9 → 54,9
*
* @return Value of CPUID[n] register.
*/
static inline __u64 cpuid_read(int n)
static inline uint64_t cpuid_read(int n)
{
__u64 v;
uint64_t v;
__asm__ volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n));
/kernel/trunk/arch/ia64/src/fpu_context.c
282,7 → 282,7
 
void fpu_enable(void)
{
__u64 a = 0 ;
uint64_t a = 0 ;
asm volatile(
"rsm %0;;"
"srlz.i\n"
304,7 → 304,7
void fpu_disable(void)
{
 
__u64 a = 0 ;
uint64_t a = 0 ;
asm volatile(
"ssm %0;;\n"
"srlz.i\n"
325,7 → 325,7
 
void fpu_init(void)
{
__u64 a = 0 ;
uint64_t a = 0 ;
asm volatile
(
"mov %0=ar.fpsr;;\n"
/kernel/trunk/arch/ia64/src/ddi/ddi.c
47,7 → 47,7
*
* @return 0 on success or an error code from errno.h.
*/
int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size)
int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size)
{
return 0;
}
/kernel/trunk/arch/ia64/src/proc/scheduler.c
50,11 → 50,11
/** Prepare kernel stack pointers in bank 0 r22 and r23 and make sure the stack is mapped in DTR. */
void before_thread_runs_arch(void)
{
__address base;
uintptr_t base;
base = ALIGN_DOWN(config.base, 1<<KERNEL_PAGE_WIDTH);
 
if ((__address) THREAD->kstack < base || (__address) THREAD->kstack > base + (1<<(KERNEL_PAGE_WIDTH))) {
if ((uintptr_t) THREAD->kstack < base || (uintptr_t) THREAD->kstack > base + (1<<(KERNEL_PAGE_WIDTH))) {
/*
* Kernel stack of this thread is not mapped by DTR[TR_KERNEL].
* Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it.
61,11 → 61,11
*/
/* purge DTR[TR_STACK1] and DTR[TR_STACK2] */
dtr_purge((__address) THREAD->kstack, PAGE_WIDTH+1);
dtr_purge((uintptr_t) THREAD->kstack, PAGE_WIDTH+1);
/* insert DTR[TR_STACK1] and DTR[TR_STACK2] */
dtlb_kernel_mapping_insert((__address) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK1);
dtlb_kernel_mapping_insert((__address) THREAD->kstack + PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, DTR_KSTACK2);
dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK1);
dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack + PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, DTR_KSTACK2);
}
/*
/kernel/trunk/arch/ia64/src/ia64.c
77,7 → 77,7
void arch_pre_mm_init(void)
{
/* Set Interruption Vector Address (i.e. location of interruption vector table). */
iva_write((__address) &ivt);
iva_write((uintptr_t) &ivt);
srlz_d();
ski_init_console();
116,10 → 116,10
rsc.pl = PL_USER;
rsc.mode = 3; /* eager mode */
 
switch_to_userspace((__address) kernel_uarg->uspace_entry,
((__address) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
((__address) kernel_uarg->uspace_stack)+PAGE_SIZE,
(__address) kernel_uarg->uspace_uarg,
switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry,
((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE,
(uintptr_t) kernel_uarg->uspace_uarg,
psr.value, rsc.value);
 
while (1) {
131,7 → 131,7
*
* We use r13 (a.k.a. tp) for this purpose.
*/
__native sys_tls_set(__native addr)
unative_t sys_tls_set(unative_t addr)
{
return 0;
}
/kernel/trunk/arch/ia64/src/ski/ski.c
44,7 → 44,7
int kbd_uspace=0;
 
static void ski_putchar(chardev_t *d, const char ch);
static __s32 ski_getchar(void);
static int32_t ski_getchar(void);
 
/** Display character on debug console
*
78,9 → 78,9
*
* @return ASCII code of pressed key or 0 if no key pressed.
*/
__s32 ski_getchar(void)
int32_t ski_getchar(void)
{
__u64 ch;
uint64_t ch;
__asm__ volatile (
"mov r15=%1\n"
92,7 → 92,7
: "r15", "r8"
);
 
return (__s32) ch;
return (int32_t) ch;
}
 
/**
/kernel/trunk/arch/ia64/src/cpu/cpu.c
51,10 → 51,10
void cpu_print_report(cpu_t *m)
{
char *family_str;
char vendor[2*sizeof(__u64)+1];
char vendor[2*sizeof(uint64_t)+1];
*((__u64 *) &vendor[0*sizeof(__u64)]) = CPU->arch.cpuid0;
*((__u64 *) &vendor[1*sizeof(__u64)]) = CPU->arch.cpuid1;
*((uint64_t *) &vendor[0*sizeof(uint64_t)]) = CPU->arch.cpuid0;
*((uint64_t *) &vendor[1*sizeof(uint64_t)]) = CPU->arch.cpuid1;
vendor[sizeof(vendor)-1] = '\0';
switch(m->arch.cpuid3.family) {
/kernel/trunk/arch/ia64/src/mm/tlb.c
57,8 → 57,8
void tlb_invalidate_all(void)
{
ipl_t ipl;
__address adr;
__u32 count1, count2, stride1, stride2;
uintptr_t adr;
uint32_t count1, count2, stride1, stride2;
int i,j;
101,7 → 101,7
}
 
 
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
region_register rr;
bool restore_rr = false;
108,7 → 108,7
int b = 0;
int c = cnt;
 
__address va;
uintptr_t va;
va = page;
 
rr.word = rr_read(VA2VRN(va));
129,7 → 129,7
while(c >>= 1)
b++;
b >>= 1;
__u64 ps;
uint64_t ps;
switch (b) {
case 0: /*cnt 1-3*/
201,7 → 201,7
* @param asid Address space identifier.
* @param entry The rest of TLB entry as required by TLB insertion format.
*/
void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry)
void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
{
tc_mapping_insert(va, asid, entry, true);
}
212,7 → 212,7
* @param asid Address space identifier.
* @param entry The rest of TLB entry as required by TLB insertion format.
*/
void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry)
void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
{
tc_mapping_insert(va, asid, entry, false);
}
224,7 → 224,7
* @param entry The rest of TLB entry as required by TLB insertion format.
* @param dtc If true, insert into data translation cache, use instruction translation cache otherwise.
*/
void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc)
void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc)
{
region_register rr;
bool restore_rr = false;
275,7 → 275,7
* @param entry The rest of TLB entry as required by TLB insertion format.
* @param tr Translation register.
*/
void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr)
void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
{
tr_mapping_insert(va, asid, entry, false, tr);
}
287,7 → 287,7
* @param entry The rest of TLB entry as required by TLB insertion format.
* @param tr Translation register.
*/
void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr)
void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
{
tr_mapping_insert(va, asid, entry, true, tr);
}
300,7 → 300,7
* @param dtr If true, insert into data translation register, use instruction translation register otherwise.
* @param tr Translation register.
*/
void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr)
void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr)
{
region_register rr;
bool restore_rr = false;
351,7 → 351,7
* @param dtr If true, insert into data translation register, use data translation cache otherwise.
* @param tr Translation register if dtr is true, ignored otherwise.
*/
void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr)
void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr)
{
tlb_entry_t entry;
380,7 → 380,7
* @param page Virtual page address including VRN bits.
* @param width Width of the purge in bits.
*/
void dtr_purge(__address page, count_t width)
void dtr_purge(uintptr_t page, count_t width)
{
__asm__ volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2));
}
444,11 → 444,11
* @param vector Interruption vector.
* @param istate Structure with saved interruption state.
*/
void alternate_instruction_tlb_fault(__u64 vector, istate_t *istate)
void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate)
{
region_register rr;
rid_t rid;
__address va;
uintptr_t va;
pte_t *t;
va = istate->cr_ifa; /* faulting address */
481,11 → 481,11
* @param vector Interruption vector.
* @param istate Structure with saved interruption state.
*/
void alternate_data_tlb_fault(__u64 vector, istate_t *istate)
void alternate_data_tlb_fault(uint64_t vector, istate_t *istate)
{
region_register rr;
rid_t rid;
__address va;
uintptr_t va;
pte_t *t;
va = istate->cr_ifa; /* faulting address */
530,7 → 530,7
* @param vector Interruption vector.
* @param istate Structure with saved interruption state.
*/
void data_nested_tlb_fault(__u64 vector, istate_t *istate)
void data_nested_tlb_fault(uint64_t vector, istate_t *istate)
{
panic("%s\n", __FUNCTION__);
}
540,11 → 540,11
* @param vector Interruption vector.
* @param istate Structure with saved interruption state.
*/
void data_dirty_bit_fault(__u64 vector, istate_t *istate)
void data_dirty_bit_fault(uint64_t vector, istate_t *istate)
{
region_register rr;
rid_t rid;
__address va;
uintptr_t va;
pte_t *t;
va = istate->cr_ifa; /* faulting address */
577,11 → 577,11
* @param vector Interruption vector.
* @param istate Structure with saved interruption state.
*/
void instruction_access_bit_fault(__u64 vector, istate_t *istate)
void instruction_access_bit_fault(uint64_t vector, istate_t *istate)
{
region_register rr;
rid_t rid;
__address va;
uintptr_t va;
pte_t *t;
 
va = istate->cr_ifa; /* faulting address */
614,11 → 614,11
* @param vector Interruption vector.
* @param istate Structure with saved interruption state.
*/
void data_access_bit_fault(__u64 vector, istate_t *istate)
void data_access_bit_fault(uint64_t vector, istate_t *istate)
{
region_register rr;
rid_t rid;
__address va;
uintptr_t va;
pte_t *t;
 
va = istate->cr_ifa; /* faulting address */
651,11 → 651,11
* @param vector Interruption vector.
* @param istate Structure with saved interruption state.
*/
void page_not_present(__u64 vector, istate_t *istate)
void page_not_present(uint64_t vector, istate_t *istate)
{
region_register rr;
rid_t rid;
__address va;
uintptr_t va;
pte_t *t;
va = istate->cr_ifa; /* faulting address */
/kernel/trunk/arch/ia64/src/mm/vhpt.c
40,22 → 40,22
 
static vhpt_entry_t* vhpt_base;
 
__address vhpt_set_up(void)
uintptr_t vhpt_set_up(void)
{
vhpt_base = frame_alloc(VHPT_WIDTH-FRAME_WIDTH,FRAME_KA | FRAME_ATOMIC);
if(!vhpt_base)
panic("Kernel configured with VHPT but no memory for table.");
vhpt_invalidate_all();
return (__address) vhpt_base;
return (uintptr_t) vhpt_base;
}
 
 
void vhpt_mapping_insert(__address va, asid_t asid, tlb_entry_t entry)
void vhpt_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
{
region_register rr_save, rr;
index_t vrn;
rid_t rid;
__u64 tag;
uint64_t tag;
 
vhpt_entry_t *ventry;
 
84,7 → 84,7
 
void vhpt_invalidate_all()
{
memsetb((__address)vhpt_base,1<<VHPT_WIDTH,0);
memsetb((uintptr_t)vhpt_base,1<<VHPT_WIDTH,0);
}
 
void vhpt_invalidate_asid(asid_t asid)
/kernel/trunk/arch/ia64/src/mm/page.c
66,7 → 66,7
pta_register pta;
int i;
#ifdef CONFIG_VHPT
__address vhpt_base;
uintptr_t vhpt_base;
#endif
 
/*
128,7 → 128,7
*
* @return VHPT entry address.
*/
vhpt_entry_t *vhpt_hash(__address page, asid_t asid)
vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid)
{
region_register rr_save, rr;
index_t vrn;
172,7 → 172,7
*
* @return True if page and asid match the page and asid of t, false otherwise.
*/
bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)
bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v)
{
region_register rr_save, rr;
index_t vrn;
216,12 → 216,12
* @param frame Physical address of the frame to wich page is mapped.
* @param flags Different flags for the mapping.
*/
void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)
void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags)
{
region_register rr_save, rr;
index_t vrn;
rid_t rid;
__u64 tag;
uint64_t tag;
 
ASSERT(v);
 
/kernel/trunk/arch/ia64/src/interrupt.c
119,10 → 119,10
"Reserved"
};
 
static char *vector_to_string(__u16 vector);
static char *vector_to_string(uint16_t vector);
static void dump_interrupted_context(istate_t *istate);
 
char *vector_to_string(__u16 vector)
char *vector_to_string(uint16_t vector)
{
ASSERT(vector <= VECTOR_MAX);
152,7 → 152,7
printf("cr.ifa=%#018llx\t(%s)\n", istate->cr_ifa, ifa);
}
 
void general_exception(__u64 vector, istate_t *istate)
void general_exception(uint64_t vector, istate_t *istate)
{
char *desc = "";
 
188,19 → 188,19
 
void fpu_enable(void);
 
void disabled_fp_register(__u64 vector, istate_t *istate)
void disabled_fp_register(uint64_t vector, istate_t *istate)
{
#ifdef CONFIG_FPU_LAZY
scheduler_fpu_lazy_request();
#else
fault_if_from_uspace(istate, "Interruption: %#hx (%s)", (__u16) vector, vector_to_string(vector));
fault_if_from_uspace(istate, "Interruption: %#hx (%s)", (uint16_t) vector, vector_to_string(vector));
dump_interrupted_context(istate);
panic("Interruption: %#hx (%s)\n", (__u16) vector, vector_to_string(vector));
panic("Interruption: %#hx (%s)\n", (uint16_t) vector, vector_to_string(vector));
#endif
}
 
 
void nop_handler(__u64 vector, istate_t *istate)
void nop_handler(uint64_t vector, istate_t *istate)
{
}
 
207,7 → 207,7
 
 
/** Handle syscall. */
int break_instruction(__u64 vector, istate_t *istate)
int break_instruction(uint64_t vector, istate_t *istate)
{
/*
* Move to next instruction after BREAK.
227,14 → 227,14
return -1;
}
 
void universal_handler(__u64 vector, istate_t *istate)
void universal_handler(uint64_t vector, istate_t *istate)
{
fault_if_from_uspace(istate,"Interruption: %#hx (%s)\n",(__u16) vector, vector_to_string(vector));
fault_if_from_uspace(istate,"Interruption: %#hx (%s)\n",(uint16_t) vector, vector_to_string(vector));
dump_interrupted_context(istate);
panic("Interruption: %#hx (%s)\n", (__u16) vector, vector_to_string(vector));
panic("Interruption: %#hx (%s)\n", (uint16_t) vector, vector_to_string(vector));
}
 
void external_interrupt(__u64 vector, istate_t *istate)
void external_interrupt(uint64_t vector, istate_t *istate)
{
cr_ivr_t ivr;
254,7 → 254,7
}
}
 
void virtual_interrupt(__u64 irq,void *param)
void virtual_interrupt(uint64_t irq,void *param)
{
switch(irq) {
case IRQ_KBD:
267,7 → 267,7
}
 
/* Reregister irq to be IPC-ready */
void irq_ipc_bind_arch(__native irq)
void irq_ipc_bind_arch(unative_t irq)
{
if(irq==IRQ_KBD) {
kbd_uspace=1;
/kernel/trunk/arch/ia64/src/drivers/it.c
71,8 → 71,8
/** Process Interval Timer interrupt. */
void it_interrupt(void)
{
__s64 c;
__s64 m;
int64_t c;
int64_t m;
eoi_write(EOI);