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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /kernel/trunk/arch/ia64/src/mm/tlb.c @ 817

  → /kernel/trunk/arch/ia64/src/mm/tlb.c @ 818

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 817 → Rev 818

/kernel/trunk/arch/ia64/src/mm/tlb.c
31,8 → 31,9
*/
#include <mm/tlb.h>
#include <arch/mm/asid.h>
#include <arch/mm/tlb.h>
/** Invalidate all TLB entries. */
void tlb_invalidate_all(void)
{
47,3 → 48,121
{
/* TODO */
}
void tlb_fill_data(__address va,asid_t asid,vhpt_entry_t entry)
{
region_register rr;
if(!(entry.not_present.p)) return;
rr.word=rr_read(VA_REGION(va));
if(rr.map.rid==ASID2RID(asid,VA_REGION(va)))
{
asm
(
"srlz.i;;\n"
"srlz.d;;\n"
"mov r8=psr;;\n"
"and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/
"mov psr.l=r9;;\n"
"srlz.d;;\n"
"srlz.i;;\n"
"mov cr20=%1\n" /*va*/ /*cr20 == IFA*/
"mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/
"itc.d %3;;\n" /*entry.word[0]*/
"mov psr.l=r8;;\n"
"srlz.d;;\n"
:
:"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
:"r8","r9"
);
}
else
{
region_register rr0;
rr0=rr;
rr0.map.rid=ASID2RID(asid,VA_REGION(va));
rr_write(VA_REGION(va),rr0.word);
asm
(
"mov r8=psr;;\n"
"and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/
"mov psr.l=r9;;\n"
"srlz.d;;\n"
"mov cr20=%1\n" /*va*/ /*cr20 == IFA*/
"mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/
"itc.d %3;;\n" /*entry.word[0]*/
"mov psr.l=r8;;\n"
"srlz.d;;\n"
:
:"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
:"r8","r9"
);
rr_write(VA_REGION(va),rr.word);
}
}
void tlb_fill_code(__address va,asid_t asid,vhpt_entry_t entry)
{
region_register rr;
if(!(entry.not_present.p)) return;
rr.word=rr_read(VA_REGION(va));
if(rr.map.rid==ASID2RID(asid,VA_REGION(va)))
{
asm
(
"srlz.i;;\n"
"srlz.d;;\n"
"mov r8=psr;;\n"
"and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/
"mov psr.l=r9;;\n"
"srlz.d;;\n"
"srlz.i;;\n"
"mov cr20=%1\n" /*va*/ /*cr20 == IFA*/
"mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/
"itc.i %3;;\n" /*entry.word[0]*/
"mov psr.l=r8;;\n"
"srlz.d;;\n"
:
:"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
:"r8","r9"
);
}
else
{
region_register rr0;
rr0=rr;
rr0.map.rid=ASID2RID(asid,VA_REGION(va));
rr_write(VA_REGION(va),rr0.word);
asm
(
"mov r8=psr;;\n"
"and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/
"mov psr.l=r9;;\n"
"srlz.d;;\n"
"mov cr20=%1\n" /*va*/ /*cr20 == IFA*/
"mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/
"itc.i %3;;\n" /*entry.word[0]*/
"mov psr.l=r8;;\n"
"srlz.d;;\n"
:
:"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
:"r8","r9"
);
rr_write(VA_REGION(va),rr.word);
}
}