Subversion Repositories HelenOS-historic

Compare Revisions

Ignore whitespace Rev 918 → Rev 919

/kernel/trunk/arch/ia64/include/asm.h
48,6 → 48,19
return v;
}
 
/** Return Processor State Register.
*
* @return PSR.
*/
static inline __u64 psr_read(void)
{
__u64 v;
__asm__ volatile ("mov %0 = psr\n" : "=r" (v));
return v;
}
 
/** Read IVA (Interruption Vector Address).
*
* @return Return location of interruption vector table.
232,11 → 245,7
*/
static inline ipl_t interrupts_read(void)
{
__u64 v;
__asm__ volatile ("mov %0 = psr\n" : "=r" (v));
return (ipl_t) v;
return (ipl_t) psr_read();
}
 
/** Disable protection key checking. */
249,4 → 258,6
extern void cpu_sleep(void);
extern void asm_delay_loop(__u32 t);
 
extern void switch_to_userspace(__address entry, __address sp, __address bsp, __u64 ipsr, __u64 rsc);
 
#endif
/kernel/trunk/arch/ia64/include/mm/as.h
31,14 → 31,14
 
#include <arch/types.h>
 
#define KERNEL_ADDRESS_SPACE_START_ARCH (__address) 0x8000000000000000
#define KERNEL_ADDRESS_SPACE_END_ARCH (__address) 0xffffffffffffffff
#define USER_ADDRESS_SPACE_START_ARCH (__address) 0x0000000000000000
#define USER_ADDRESS_SPACE_END_ARCH (__address) 0x7fffffffffffffff
#define KERNEL_ADDRESS_SPACE_START_ARCH (__address) 0xe000000000000000ULL
#define KERNEL_ADDRESS_SPACE_END_ARCH (__address) 0xffffffffffffffffULL
#define USER_ADDRESS_SPACE_START_ARCH (__address) 0x0000000000000000ULL
#define USER_ADDRESS_SPACE_END_ARCH (__address) 0xdfffffffffffffffULL
 
#define UTEXT_ADDRESS_ARCH 0x0000000000001000
#define USTACK_ADDRESS_ARCH (0x7fffffffffffffff-(PAGE_SIZE-1))
#define UDATA_ADDRESS_ARCH 0x0000000001001000
#define UTEXT_ADDRESS_ARCH 0x0000000000010000ULL
#define USTACK_ADDRESS_ARCH 0x0000000ff0000000ULL
#define UDATA_ADDRESS_ARCH 0x0000000001010000ULL
 
extern void as_arch_init(void);
 
/kernel/trunk/arch/ia64/include/context.h
30,6 → 30,7
#define __ia64_CONTEXT_H__
 
#include <arch/types.h>
#include <arch/register.h>
#include <typedefs.h>
#include <align.h>
#include <arch/stack.h>
42,8 → 43,6
*/
#define SP_DELTA (0+ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT))
 
#define PFM_MASK (~0x3fffffffff)
 
#ifdef context_set
#undef context_set
#endif
/kernel/trunk/arch/ia64/include/register.h
29,10 → 29,6
#ifndef __ia64_REGISTER_H__
#define __ia64_REGISTER_H__
 
#ifndef __ASM__
#include <arch/types.h>
#endif
 
#define CR_IVR_MASK 0xf
#define PSR_IC_MASK 0x2000
#define PSR_I_MASK 0x4000
45,6 → 41,11
#define PSR_CPL_SHIFT 32
#define PSR_CPL_MASK_SHIFTED 3
 
#define PFM_MASK (~0x3fffffffff)
 
#define RSC_MODE_MASK 3
#define RSC_PL_MASK 12
 
/** Application registers. */
#define AR_KR0 0
#define AR_KR1 1
120,6 → 121,65
/* CR82-CR127 reserved */
 
#ifndef __ASM__
 
#include <arch/types.h>
 
/** Processor Status Register. */
union psr {
__u64 value;
struct {
unsigned : 1;
unsigned be : 1; /**< Big-Endian data accesses. */
unsigned up : 1; /**< User Performance monitor enable. */
unsigned ac : 1; /**< Alignment Check. */
unsigned mfl : 1; /**< Lower floating-point register written. */
unsigned mfh : 1; /**< Upper floating-point register written. */
unsigned : 7;
unsigned ic : 1; /**< Interruption Collection. */
unsigned i : 1; /**< Interrupt Bit. */
unsigned pk : 1; /**< Protection Key enable. */
unsigned : 1;
unsigned dt : 1; /**< Data address Translation. */
unsigned dfl : 1; /**< Disabled Floating-point Low register set. */
unsigned dfh : 1; /**< Disabled Floating-point High register set. */
unsigned sp : 1; /**< Secure Performance monitors. */
unsigned pp : 1; /**< Privileged Performance monitor enable. */
unsigned di : 1; /**< Disable Instruction set transition. */
unsigned si : 1; /**< Secure Interval timer. */
unsigned db : 1; /**< Debug Breakpoint fault. */
unsigned lp : 1; /**< Lower Privilege transfer trap. */
unsigned tb : 1; /**< Taken Branch trap. */
unsigned rt : 1; /**< Register Stack Translation. */
unsigned : 4;
unsigned cpl : 2; /**< Current Privilege Level. */
unsigned is : 1; /**< Instruction Set. */
unsigned mc : 1; /**< Machine Check abort mask. */
unsigned it : 1; /**< Instruction address Translation. */
unsigned id : 1; /**< Instruction Debug fault disable. */
unsigned da : 1; /**< Disable Data Access and Dirty-bit faults. */
unsigned dd : 1; /**< Data Debug fault disable. */
unsigned ss : 1; /**< Single Step enable. */
unsigned ri : 2; /**< Restart Instruction. */
unsigned ed : 1; /**< Exception Deferral. */
unsigned bn : 1; /**< Register Bank. */
unsigned ia : 1; /**< Disable Instruction Access-bit faults. */
} __attribute__ ((packed));
};
typedef union psr psr_t;
 
/** Register Stack Configuration Register */
union rsc {
__u64 value;
struct {
unsigned mode : 2;
unsigned pl : 2; /**< Privilege Level. */
unsigned be : 1; /**< Big-endian. */
unsigned : 11;
unsigned loadrs : 14;
} __attribute__ ((packed));
};
typedef union rsc rsc_t;
 
/** External Interrupt Vector Register */
union cr_ivr {
__u8 vector;