Subversion Repositories HelenOS-historic

Compare Revisions

Ignore whitespace Rev 1766 → Rev 1780

/kernel/trunk/arch/ia32/src/ia32.c
132,7 → 132,7
* TLS pointer is set in GS register. That means, the GS contains
* selector, and the descriptor->base is the correct address.
*/
__native sys_tls_set(__native addr)
unative_t sys_tls_set(unative_t addr)
{
THREAD->arch.tls = addr;
set_tls_desc(addr);
/kernel/trunk/arch/ia32/src/fpu_context.c
108,7 → 108,7
 
void fpu_init()
{
__u32 help0=0,help1=0;
uint32_t help0=0,help1=0;
__asm__ volatile (
"fninit;\n"
"stmxcsr %0\n"
/kernel/trunk/arch/ia32/src/cpu/cpu.c
98,10 → 98,10
cpuid_feature_info fi;
cpuid_extended_feature_info efi;
cpu_info_t info;
__u32 help = 0;
uint32_t help = 0;
CPU->arch.tss = tss_p;
CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss);
CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);
 
CPU->fpu_owner = NULL;
 
/kernel/trunk/arch/ia32/src/bios/bios.c
35,12 → 35,12
#include <arch/bios/bios.h>
#include <arch/types.h>
 
__address ebda = 0;
uintptr_t ebda = 0;
 
void bios_init(void)
{
/* Copy the EBDA address out from BIOS Data Area */
ebda = *((__u16 *) BIOS_EBDA_PTR) * 0x10;
ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10;
}
 
/** @}
/kernel/trunk/arch/ia32/src/pm.c
86,10 → 86,10
tss_t *tss_p = NULL;
 
/* gdtr is changed by kmp before next CPU is initialized */
ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) };
ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (__address) gdt };
ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
 
void gdt_setbase(descriptor_t *d, __address base)
void gdt_setbase(descriptor_t *d, uintptr_t base)
{
d->base_0_15 = base & 0xffff;
d->base_16_23 = ((base) >> 16) & 0xff;
96,13 → 96,13
d->base_24_31 = ((base) >> 24) & 0xff;
}
 
void gdt_setlimit(descriptor_t *d, __u32 limit)
void gdt_setlimit(descriptor_t *d, uint32_t limit)
{
d->limit_0_15 = limit & 0xffff;
d->limit_16_19 = (limit >> 16) & 0xf;
}
 
void idt_setoffset(idescriptor_t *d, __address offset)
void idt_setoffset(idescriptor_t *d, uintptr_t offset)
{
/*
* Offset is a linear address.
113,7 → 113,7
 
void tss_initialize(tss_t *t)
{
memsetb((__address) t, sizeof(struct tss), 0);
memsetb((uintptr_t) t, sizeof(struct tss), 0);
}
 
/*
139,7 → 139,7
d->access |= DPL_USER;
}
idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size);
exc_register(i, "undef", (iroutine) null_interrupt);
}
exc_register(13, "gp_fault", (iroutine) gp_fault);
182,7 → 182,7
* Update addresses in GDT and IDT to their virtual counterparts.
*/
idtr.limit = sizeof(idt);
idtr.base = (__address) idt;
idtr.base = (uintptr_t) idt;
gdtr_load(&gdtr);
idtr_load(&idtr);
211,7 → 211,7
gdt_p[TSS_DES].special = 1;
gdt_p[TSS_DES].granularity = 0;
gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
 
/*
224,7 → 224,7
clean_AM_flag(); /* Disable alignment check */
}
 
void set_tls_desc(__address tls)
void set_tls_desc(uintptr_t tls)
{
ptr_16_32_t cpugdtr;
descriptor_t *gdt_p;
/kernel/trunk/arch/ia32/src/smp/mps.c
55,11 → 55,11
#define FS_SIGNATURE 0x5f504d5f
#define CT_SIGNATURE 0x504d4350
 
int mps_fs_check(__u8 *base);
int mps_fs_check(uint8_t *base);
int mps_ct_check(void);
 
int configure_via_ct(void);
int configure_via_default(__u8 n);
int configure_via_default(uint8_t n);
 
int ct_processor_entry(struct __processor_entry *pr);
void ct_bus_entry(struct __bus_entry *bus);
92,7 → 92,7
static count_t get_cpu_count(void);
static bool is_cpu_enabled(index_t i);
static bool is_bsp(index_t i);
static __u8 get_cpu_apic_id(index_t i);
static uint8_t get_cpu_apic_id(index_t i);
static int mps_irq_to_pin(int irq);
 
struct smp_config_operations mps_config_operations = {
120,7 → 120,7
return processor_entries[i].cpu_flags & 0x2;
}
 
__u8 get_cpu_apic_id(index_t i)
uint8_t get_cpu_apic_id(index_t i)
{
ASSERT(i < processor_entry_cnt);
return processor_entries[i].l_apic_id;
130,10 → 130,10
/*
* Used to check the integrity of the MP Floating Structure.
*/
int mps_fs_check(__u8 *base)
int mps_fs_check(uint8_t *base)
{
int i;
__u8 sum;
uint8_t sum;
for (i = 0, sum = 0; i < 16; i++)
sum += base[i];
146,9 → 146,9
*/
int mps_ct_check(void)
{
__u8 *base = (__u8 *) ct;
__u8 *ext = base + ct->base_table_length;
__u8 sum;
uint8_t *base = (uint8_t *) ct;
uint8_t *ext = base + ct->base_table_length;
uint8_t sum;
int i;
/* count the checksum for the base table */
167,7 → 167,7
 
void mps_init(void)
{
__u8 *addr[2] = { NULL, (__u8 *) PA2KA(0xf0000) };
uint8_t *addr[2] = { NULL, (uint8_t *) PA2KA(0xf0000) };
int i, j, length[2] = { 1024, 64*1024 };
 
178,10 → 178,10
* 2. search 64K starting at 0xf0000
*/
 
addr[0] = (__u8 *) PA2KA(ebda ? ebda : 639 * 1024);
addr[0] = (uint8_t *) PA2KA(ebda ? ebda : 639 * 1024);
for (i = 0; i < 2; i++) {
for (j = 0; j < length[i]; j += 16) {
if (*((__u32 *) &addr[i][j]) == FS_SIGNATURE && mps_fs_check(&addr[i][j])) {
if (*((uint32_t *) &addr[i][j]) == FS_SIGNATURE && mps_fs_check(&addr[i][j])) {
fs = (struct mps_fs *) &addr[i][j];
goto fs_found;
}
199,7 → 199,7
return;
}
 
ct = (struct mps_ct *)PA2KA((__address)fs->configuration_table);
ct = (struct mps_ct *)PA2KA((uintptr_t)fs->configuration_table);
config.cpu_count = configure_via_ct();
}
else
210,7 → 210,7
 
int configure_via_ct(void)
{
__u8 *cur;
uint8_t *cur;
int i, cnt;
if (ct->signature != CT_SIGNATURE) {
226,7 → 226,7
return 1;
}
l_apic = (__u32 *)(__address)ct->l_apic;
l_apic = (uint32_t *)(uintptr_t)ct->l_apic;
 
cnt = 0;
cur = &ct->base_table[0];
289,7 → 289,7
return cnt;
}
 
int configure_via_default(__u8 n)
int configure_via_default(uint8_t n)
{
/*
* Not yet implemented.
336,7 → 336,7
return;
}
io_apic = (__u32 *)(__address)ioa->io_apic;
io_apic = (uint32_t *)(uintptr_t)ioa->io_apic;
}
 
//#define MPSCT_VERBOSE
404,8 → 404,8
 
void ct_extended_entries(void)
{
__u8 *ext = (__u8 *) ct + ct->base_table_length;
__u8 *cur;
uint8_t *ext = (uint8_t *) ct + ct->base_table_length;
uint8_t *cur;
 
for (cur = ext; cur < ext + ct->ext_table_length; cur += cur[CT_EXT_ENTRY_LEN]) {
switch (cur[CT_EXT_ENTRY_TYPE]) {
/kernel/trunk/arch/ia32/src/smp/smp.c
61,7 → 61,7
 
void smp_init(void)
{
__address l_apic_address, io_apic_address;
uintptr_t l_apic_address, io_apic_address;
 
if (acpi_madt) {
acpi_madt_parse();
72,22 → 72,22
ops = &mps_config_operations;
}
 
l_apic_address = (__address) frame_alloc(ONE_FRAME, FRAME_ATOMIC | FRAME_KA);
l_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_ATOMIC | FRAME_KA);
if (!l_apic_address)
panic("cannot allocate address for l_apic\n");
 
io_apic_address = (__address) frame_alloc(ONE_FRAME, FRAME_ATOMIC | FRAME_KA);
io_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_ATOMIC | FRAME_KA);
if (!io_apic_address)
panic("cannot allocate address for io_apic\n");
 
if (config.cpu_count > 1) {
page_mapping_insert(AS_KERNEL, l_apic_address, (__address) l_apic,
page_mapping_insert(AS_KERNEL, l_apic_address, (uintptr_t) l_apic,
PAGE_NOT_CACHEABLE);
page_mapping_insert(AS_KERNEL, io_apic_address, (__address) io_apic,
page_mapping_insert(AS_KERNEL, io_apic_address, (uintptr_t) io_apic,
PAGE_NOT_CACHEABLE);
l_apic = (__u32 *) l_apic_address;
io_apic = (__u32 *) io_apic_address;
l_apic = (uint32_t *) l_apic_address;
io_apic = (uint32_t *) io_apic_address;
}
}
 
114,8 → 114,8
/*
* Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot()
*/
*((__u16 *) (PA2KA(0x467+0))) = ((__address) ap_boot) >> 4; /* segment */
*((__u16 *) (PA2KA(0x467+2))) = 0; /* offset */
*((uint16_t *) (PA2KA(0x467+0))) = ((uintptr_t) ap_boot) >> 4; /* segment */
*((uint16_t *) (PA2KA(0x467+2))) = 0; /* offset */
/*
* Save 0xa to address 0xf of the CMOS RAM.
154,10 → 154,10
panic("couldn't allocate memory for GDT\n");
 
memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(struct descriptor));
memsetb((__address)(&gdt_new[TSS_DES]), sizeof(struct descriptor), 0);
memsetb((uintptr_t)(&gdt_new[TSS_DES]), sizeof(struct descriptor), 0);
protected_ap_gdtr.limit = GDT_ITEMS * sizeof(struct descriptor);
protected_ap_gdtr.base = KA2PA((__address) gdt_new);
gdtr.base = (__address) gdt_new;
protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new);
gdtr.base = (uintptr_t) gdt_new;
 
if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) {
/*
/kernel/trunk/arch/ia32/src/smp/ap.S
69,7 → 69,7
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
movl $KA2PA(ctx), %eax # KA2PA((__address) &ctx)
movl $KA2PA(ctx), %eax # KA2PA((uintptr_t) &ctx)
movl (%eax), %esp
subl $0x80000000, %esp # KA2PA(ctx.sp)
 
/kernel/trunk/arch/ia32/src/smp/ipi.c
39,7 → 39,7
 
void ipi_broadcast_arch(int ipi)
{
(void) l_apic_broadcast_custom_ipi((__u8) ipi);
(void) l_apic_broadcast_custom_ipi((uint8_t) ipi);
}
 
#endif /* CONFIG_SMP */
/kernel/trunk/arch/ia32/src/smp/apic.c
67,10 → 67,10
* optimize the code too much and accesses to l_apic and io_apic, that must
* always be 32-bit, would use byte oriented instructions.
*/
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
 
__u32 apic_id_mask = 0;
uint32_t apic_id_mask = 0;
 
static int apic_poll_errors(void);
 
218,7 → 218,7
*
* @return 0 on failure, 1 on success.
*/
int l_apic_broadcast_custom_ipi(__u8 vector)
int l_apic_broadcast_custom_ipi(uint8_t vector)
{
icr_t icr;
 
248,7 → 248,7
*
* @return 0 on failure, 1 on success.
*/
int l_apic_send_init_ipi(__u8 apicid)
int l_apic_send_init_ipi(uint8_t apicid)
{
icr_t icr;
int i;
305,7 → 305,7
*/
for (i = 0; i<2; i++) {
icr.lo = l_apic[ICRlo];
icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */
icr.delmod = DELMOD_STARTUP;
icr.destmod = DESTMOD_PHYS;
icr.level = LEVEL_ASSERT;
331,7 → 331,7
lvt_tm_t tm;
ldr_t ldr;
dfr_t dfr;
__u32 t1, t2;
uint32_t t1, t2;
 
/* Initialize LVT Error register. */
error.value = l_apic[LVT_Err];
455,7 → 455,7
*
* @return Local APIC ID.
*/
__u8 l_apic_id(void)
uint8_t l_apic_id(void)
{
l_apic_id_t idreg;
469,7 → 469,7
*
* @return Content of the addressed IO APIC register.
*/
__u32 io_apic_read(__u8 address)
uint32_t io_apic_read(uint8_t address)
{
io_regsel_t regsel;
484,7 → 484,7
* @param address IO APIC register address.
* @param x Content to be written to the addressed IO APIC register.
*/
void io_apic_write(__u8 address, __u32 x)
void io_apic_write(uint8_t address, uint32_t x)
{
io_regsel_t regsel;
501,7 → 501,7
* @param v Interrupt vector to trigger.
* @param flags Flags.
*/
void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags)
{
io_redirection_reg_t reg;
int dlvr = DELMOD_FIXED;
527,7 → 527,7
*
* @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
*/
void io_apic_disable_irqs(__u16 irqmask)
void io_apic_disable_irqs(uint16_t irqmask)
{
io_redirection_reg_t reg;
int i, pin;
553,7 → 553,7
*
* @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
*/
void io_apic_enable_irqs(__u16 irqmask)
void io_apic_enable_irqs(uint16_t irqmask)
{
int i, pin;
io_redirection_reg_t reg;
/kernel/trunk/arch/ia32/src/ddi/ddi.c
56,7 → 56,7
*
* @return 0 on success or an error code from errno.h.
*/
int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size)
int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size)
{
count_t bits;
 
66,13 → 66,13
 
if (task->arch.iomap.bits < bits) {
bitmap_t oldiomap;
__u8 *newmap;
uint8_t *newmap;
/*
* The I/O permission bitmap is too small and needs to be grown.
*/
newmap = (__u8 *) malloc(BITS2BYTES(bits), FRAME_ATOMIC);
newmap = (uint8_t *) malloc(BITS2BYTES(bits), FRAME_ATOMIC);
if (!newmap)
return ENOMEM;
/kernel/trunk/arch/ia32/src/proc/scheduler.c
58,7 → 58,7
*/
void before_thread_runs_arch(void)
{
CPU->arch.tss->esp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
CPU->arch.tss->esp0 = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
CPU->arch.tss->ss0 = selector(KDATA_DES);
 
/* Set up TLS in GS register */
/kernel/trunk/arch/ia32/src/mm/tlb.c
59,7 → 59,7
* @param page Address of the first page whose entry is to be invalidated.
* @param cnt Number of entries to invalidate.
*/
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
int i;
 
/kernel/trunk/arch/ia32/src/mm/frame.c
51,7 → 51,7
size_t hardcoded_unmapped_ktext_size = 0;
size_t hardcoded_unmapped_kdata_size = 0;
 
__address last_frame = 0;
uintptr_t last_frame = 0;
 
static void init_e820_memory(pfn_t minconf)
{
99,9 → 99,9
else
name = "invalid";
printf("%.*p %#.16llXB %s\n",
sizeof(__native) * 2,
(__native) e820table[i].base_address,
(__u64) e820table[i].size,
sizeof(unative_t) * 2,
(unative_t) e820table[i].base_address,
(uint64_t) e820table[i].size,
name);
}
return 0;
/kernel/trunk/arch/ia32/src/mm/memory_init.c
37,9 → 37,9
#include <arch/mm/page.h>
#include <print.h>
 
__u8 e820counter = 0xff;
uint8_t e820counter = 0xff;
struct e820memmap_ e820table[MEMMAP_E820_MAX_RECORDS];
__u32 e801memorysize;
uint32_t e801memorysize;
 
size_t get_memory_size(void)
{
48,7 → 48,7
 
void memory_print_map(void)
{
__u8 i;
uint8_t i;
for (i=0;i<e820counter;i++) {
printf("E820 base: %#.16llx size: %#.16llx type: ", e820table[i].base_address, e820table[i].size);
/kernel/trunk/arch/ia32/src/mm/page.c
51,7 → 51,7
 
void page_arch_init(void)
{
__address cur;
uintptr_t cur;
int flags;
 
if (config.cpu_active == 1) {
68,10 → 68,10
}
 
exc_register(14, "page_fault", (iroutine) page_fault);
write_cr3((__address) AS_KERNEL->page_table);
write_cr3((uintptr_t) AS_KERNEL->page_table);
}
else {
write_cr3((__address) AS_KERNEL->page_table);
write_cr3((uintptr_t) AS_KERNEL->page_table);
}
 
paging_on();
78,12 → 78,12
}
 
 
__address hw_map(__address physaddr, size_t size)
uintptr_t hw_map(uintptr_t physaddr, size_t size)
{
if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
panic("Unable to map physical memory %p (%d bytes)", physaddr, size)
__address virtaddr = PA2KA(last_frame);
uintptr_t virtaddr = PA2KA(last_frame);
pfn_t i;
for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++)
page_mapping_insert(AS_KERNEL, virtaddr + PFN2ADDR(i), physaddr + PFN2ADDR(i), PAGE_NOT_CACHEABLE);
95,7 → 95,7
 
void page_fault(int n, istate_t *istate)
{
__address page;
uintptr_t page;
pf_access_t access;
page = read_cr2();
/kernel/trunk/arch/ia32/src/interrupt.c
56,8 → 56,8
* Interrupt and exception dispatching.
*/
 
void (* disable_irqs_function)(__u16 irqmask) = NULL;
void (* enable_irqs_function)(__u16 irqmask) = NULL;
void (* disable_irqs_function)(uint16_t irqmask) = NULL;
void (* enable_irqs_function)(uint16_t irqmask) = NULL;
void (* eoi_function)(void) = NULL;
 
void PRINT_INFO_ERRCODE(istate_t *istate)
129,7 → 129,7
 
void simd_fp_exception(int n, istate_t *istate)
{
__u32 mxcsr;
uint32_t mxcsr;
asm
(
"stmxcsr %0;\n"
136,10 → 136,10
:"=m"(mxcsr)
);
fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx",
(__native)mxcsr);
(unative_t)mxcsr);
 
PRINT_INFO_ERRCODE(istate);
printf("MXCSR: %#zx\n",(__native)(mxcsr));
printf("MXCSR: %#zx\n",(unative_t)(mxcsr));
panic("SIMD FP exception(19)\n");
}
 
164,7 → 164,7
tlb_shootdown_ipi_recv();
}
 
void trap_virtual_enable_irqs(__u16 irqmask)
void trap_virtual_enable_irqs(uint16_t irqmask)
{
if (enable_irqs_function)
enable_irqs_function(irqmask);
172,7 → 172,7
panic("no enable_irqs_function\n");
}
 
void trap_virtual_disable_irqs(__u16 irqmask)
void trap_virtual_disable_irqs(uint16_t irqmask)
{
if (disable_irqs_function)
disable_irqs_function(irqmask);
197,7 → 197,7
 
 
/* Reregister irq to be IPC-ready */
void irq_ipc_bind_arch(__native irq)
void irq_ipc_bind_arch(unative_t irq)
{
if (irq == IRQ_CLK)
return;
/kernel/trunk/arch/ia32/src/drivers/vesa.c
50,11 → 50,11
#include <memstr.h>
#include <bitops.h>
 
__u32 vesa_ph_addr;
__u16 vesa_width;
__u16 vesa_height;
__u16 vesa_bpp;
__u16 vesa_scanline;
uint32_t vesa_ph_addr;
uint16_t vesa_width;
uint16_t vesa_height;
uint16_t vesa_bpp;
uint16_t vesa_scanline;
 
int vesa_present(void)
{
/kernel/trunk/arch/ia32/src/drivers/i8259.c
89,9 → 89,9
pic_enable_irqs(1<<IRQ_PIC1); /* but enable pic1 */
}
 
void pic_enable_irqs(__u16 irqmask)
void pic_enable_irqs(uint16_t irqmask)
{
__u8 x;
uint8_t x;
 
if (irqmask & 0xff) {
x = inb(PIC_PIC0PORT2);
103,9 → 103,9
}
}
 
void pic_disable_irqs(__u16 irqmask)
void pic_disable_irqs(uint16_t irqmask)
{
__u8 x;
uint8_t x;
 
if (irqmask & 0xff) {
x = inb(PIC_PIC0PORT2);
/kernel/trunk/arch/ia32/src/drivers/i8254.c
78,9 → 78,9
#define SHIFT 11
void i8254_calibrate_delay_loop(void)
{
__u64 clk1, clk2;
__u32 t1, t2, o1, o2;
__u8 not_ok;
uint64_t clk1, clk2;
uint32_t t1, t2, o1, o2;
uint8_t not_ok;
 
 
/*
/kernel/trunk/arch/ia32/src/drivers/ega.c
53,8 → 53,8
*/
 
SPINLOCK_INITIALIZE(egalock);
static __u32 ega_cursor;
static __u8 *videoram;
static uint32_t ega_cursor;
static uint8_t *videoram;
 
static void ega_putchar(chardev_t *d, const char ch);
 
67,9 → 67,9
 
void ega_init(void)
{
__u8 hi, lo;
uint8_t hi, lo;
videoram = (__u8 *) hw_map(VIDEORAM, SCREEN * 2);
videoram = (uint8_t *) hw_map(VIDEORAM, SCREEN * 2);
outb(0x3d4, 0xe);
hi = inb(0x3d5);
outb(0x3d4, 0xf);
104,7 → 104,7
return;
 
memcpy((void *) videoram, (void *) (videoram + ROW * 2), (SCREEN - ROW) * 2);
memsetw((__address) (videoram + (SCREEN - ROW) * 2), ROW, 0x0720);
memsetw((uintptr_t) (videoram + (SCREEN - ROW) * 2), ROW, 0x0720);
ega_cursor = ega_cursor - ROW;
}