| 178,8 → 178,8 |
|---|
| */ |
| idtr.limit = sizeof(idt); |
| idtr.base = (__address) idt; |
| __asm__ volatile ("lgdt %0\n" : : "m" (gdtr)); |
| __asm__ volatile ("lidt %0\n" : : "m" (idtr)); |
| gdtr_load(&gdtr); |
| idtr_load(&idtr); |
| |
| /* |
| * Each CPU has its private GDT and TSS. |
| 213,7 → 213,7 |
|---|
| * As of this moment, the current CPU has its own GDT pointing |
| * to its own TSS. We just need to load the TR register. |
| */ |
| __asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES))); |
| tr_load(selector(TSS_DES)); |
| |
| clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */ |
| clean_AM_flag(); /* Disable alignment check */ |
| 224,9 → 224,8 |
|---|
| struct ptr_16_32 cpugdtr; |
| struct descriptor *gdt_p = (struct descriptor *) cpugdtr.base; |
| |
| __asm__ volatile ("sgdt %0\n" : : "m" (cpugdtr)); |
| |
| gdtr_store(&cpugdtr); |
| gdt_setbase(&gdt_p[TLS_DES], tls); |
| /* Reload gdt register to update GS in CPU */ |
| __asm__ volatile ("lgdt %0\n" : : "m" (cpugdtr)); |
| gdtr_load(&cpugdtr); |
| } |