| /kernel/trunk/arch/amd64/include/atomic.h |
|---|
| 101,7 → 101,7 |
| __asm__ volatile ( |
| "0:;" |
| #ifdef CONFIG_HT |
| "pause;" /* Pentium 4's HT love this instruction */ |
| "pause;" |
| #endif |
| "mov %0, %1;" |
| "testq %1, %1;" |
| /kernel/trunk/arch/amd64/src/amd64.c |
|---|
| 163,12 → 163,12 |
| i8254_normal_operation(); |
| } |
| /** Set Thread-local-storeage pointer |
| /** Set thread-local-storage pointer |
| * |
| * TLS pointer is set in FS register. Unfortunately the 64-bit |
| * part can be set only in CPL0 mode. |
| * |
| * The specs says, that on %fs:0 there is stored contents of %fs register, |
| * The specs say, that on %fs:0 there is stored contents of %fs register, |
| * we need not to go to CPL0 to read it. |
| */ |
| __native sys_tls_set(__native addr) |
| /kernel/trunk/arch/amd64/src/asm_utils.S |
|---|
| 180,8 → 180,7 |
| * Both versions have to be of the same size. amd64 assembly is, however, |
| * a little bit tricky. For instance, subq $0x80, %rsp and subq $0x78, %rsp |
| * can result in two instructions with different op-code lengths. |
| * Therefore, pay special attention to the extra NOP's that serve as |
| * a necessary fill. |
| * Therefore we align the interrupt handlers. |
| */ |
| .iflt \i-32 |