123,13 → 123,13 |
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idescriptor_t idt[IDT_ITEMS]; |
|
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt }; |
ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt }; |
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (uint64_t) gdt }; |
ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (uint64_t) idt }; |
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static tss_t tss; |
tss_t *tss_p = NULL; |
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void gdt_tss_setbase(descriptor_t *d, __address base) |
void gdt_tss_setbase(descriptor_t *d, uintptr_t base) |
{ |
tss_descriptor_t *td = (tss_descriptor_t *) d; |
|
139,7 → 139,7 |
td->base_32_63 = ((base) >> 32); |
} |
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void gdt_tss_setlimit(descriptor_t *d, __u32 limit) |
void gdt_tss_setlimit(descriptor_t *d, uint32_t limit) |
{ |
struct tss_descriptor *td = (tss_descriptor_t *) d; |
|
147,7 → 147,7 |
td->limit_16_19 = (limit >> 16) & 0xf; |
} |
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void idt_setoffset(idescriptor_t *d, __address offset) |
void idt_setoffset(idescriptor_t *d, uintptr_t offset) |
{ |
/* |
* Offset is a linear address. |
159,7 → 159,7 |
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void tss_initialize(tss_t *t) |
{ |
memsetb((__address) t, sizeof(tss_t), 0); |
memsetb((uintptr_t) t, sizeof(tss_t), 0); |
} |
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/* |
179,7 → 179,7 |
d->present = 1; |
d->type = AR_INTERRUPT; /* masking interrupt */ |
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idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size); |
idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size); |
exc_register(i, "undef", (iroutine)null_interrupt); |
} |
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214,7 → 214,7 |
/* We are going to use malloc, which may return |
* non boot-mapped pointer, initialize the CR3 register |
* ahead of page_init */ |
write_cr3((__address) AS_KERNEL->page_table); |
write_cr3((uintptr_t) AS_KERNEL->page_table); |
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tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
if (!tss_p) |
228,7 → 228,7 |
tss_desc->type = AR_TSS; |
tss_desc->dpl = PL_KERNEL; |
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gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p); |
gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p); |
gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); |
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gdtr_load(&gdtr); |