/kernel/trunk/arch/amd64/include/interrupt.h |
---|
53,6 → 53,7 |
#error Wrong definition of VECTOR_APIC_SPUR |
#endif |
#define VECTOR_DEBUG 1 |
#define VECTOR_PIC_SPUR (IVT_IRQBASE+IRQ_PIC_SPUR) |
#define VECTOR_CLK (IVT_IRQBASE+IRQ_CLK) |
#define VECTOR_KBD (IVT_IRQBASE+IRQ_KBD) |
/kernel/trunk/arch/amd64/include/asm.h |
---|
141,56 → 141,6 |
return v; |
} |
/** Read CR0 |
* |
* Return value in CR0 |
* |
* @return Value read. |
*/ |
static inline __u64 read_cr0(void) |
{ |
__u64 v; |
__asm__ volatile ("movq %%cr0,%0\n" : "=r" (v)); |
return v; |
} |
/** Read CR2 |
* |
* Return value in CR2 |
* |
* @return Value read. |
*/ |
static inline __u64 read_cr2(void) |
{ |
__u64 v; |
__asm__ volatile ("movq %%cr2,%0\n" : "=r" (v)); |
return v; |
} |
/** Write CR3 |
* |
* Write value to CR3. |
* |
* @param v Value to be written. |
*/ |
static inline void write_cr3(__u64 v) |
{ |
__asm__ volatile ("movq %0,%%cr3\n" : : "r" (v)); |
} |
/** Read CR3 |
* |
* Return value in CR3 |
* |
* @return Value read. |
*/ |
static inline __u64 read_cr3(void) |
{ |
__u64 v; |
__asm__ volatile ("movq %%cr3,%0" : "=r" (v)); |
return v; |
} |
/** Write to MSR */ |
static inline void write_msr(__u32 msr, __u64 value) |
{ |
250,6 → 200,38 |
__asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr))); |
} |
#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \ |
{ \ |
__native res; \ |
__asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \ |
return res; \ |
} |
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \ |
{ \ |
__asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \ |
} |
GEN_READ_REG(cr0); |
GEN_READ_REG(cr2); |
GEN_READ_REG(cr3); |
GEN_WRITE_REG(cr3); |
GEN_READ_REG(dr0); |
GEN_READ_REG(dr1); |
GEN_READ_REG(dr2); |
GEN_READ_REG(dr3); |
GEN_READ_REG(dr6); |
GEN_READ_REG(dr7); |
GEN_WRITE_REG(dr0); |
GEN_WRITE_REG(dr1); |
GEN_WRITE_REG(dr2); |
GEN_WRITE_REG(dr3); |
GEN_WRITE_REG(dr6); |
GEN_WRITE_REG(dr7); |
extern size_t interrupt_handler_size; |
extern void interrupt_handlers(void); |
/kernel/trunk/arch/amd64/include/debugger.h |
---|
0,0 → 1,48 |
/* |
* Copyright (C) 2006 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __amd64_DEBUGGER_H__ |
#define __amd64_DEBUGGER_H__ |
#include <arch/types.h> |
#define BKPOINTS_MAX 4 |
/* Flags that are passed to breakpoint_add function */ |
#define BKPOINT_INSTR 0x1 |
#define BKPOINT_WRITE 0x2 |
#define BKPOINT_READ_WRITE 0x4 |
#define BKPOINT_CHECK_ZERO 0x8 |
extern void debugger_init(void); |
extern int breakpoint_add(void * where, int flags); |
extern void breakpoint_del(int slot); |
#endif |
/kernel/trunk/arch/amd64/include/cpu.h |
---|
29,6 → 29,7 |
#ifndef __amd64_CPU_H__ |
#define __amd64_CPU_H__ |
#define RFLAGS_RF (1 << 16) |
#define EFER_MSR_NUM 0xc0000080 |
#define AMD_SCE_FLAG 0 |