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• This comparison shows the changes necessary to convert path

  → /kernel/trunk/ @ 1185

  → /kernel/trunk/ @ 1186

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 1185 → Rev 1186

/kernel/trunk/arch/amd64/include/asm.h
29,6 → 29,7
#ifndef __amd64_ASM_H__
#define __amd64_ASM_H__
#include <arch/pm.h>
#include <arch/types.h>
#include <config.h>
197,9 → 198,45
*/
static inline void invlpg(__address addr)
{
__asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr)));
__asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr)));
}
/** Load GDTR register from memory.
*
* @param gdtr_reg Address of memory from where to load GDTR.
*/
static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
{
__asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg));
}
/** Store GDTR register to memory.
*
* @param gdtr_reg Address of memory to where to load GDTR.
*/
static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
{
__asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg));
}
/** Load IDTR register from memory.
*
* @param idtr_reg Address of memory from where to load IDTR.
*/
static inline void idtr_load(struct ptr_16_64 *idtr_reg)
{
__asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg));
}
/** Load TR from descriptor table.
*
* @param sel Selector specifying descriptor of TSS segment.
*/
static inline void tr_load(__u16 sel)
{
__asm__ volatile ("ltr %0" : : "r" (sel));
}
#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
{ \
__native res; \

/kernel/trunk/arch/amd64/src/pm.c
215,11 → 215,11
gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
__asm__("lgdt %0" : : "m"(gdtr));
__asm__("lidt %0" : : "m"(idtr));
gdtr_load(&gdtr);
idtr_load(&idtr);
/*
* As of this moment, the current CPU has its own GDT pointing
* to its own TSS. We just need to load the TR register.
*/
__asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));
tr_load(gdtselector(TSS_DES));
}

/kernel/trunk/arch/ia32/include/asm.h
30,6 → 30,7
#ifndef __ia32_ASM_H__
#define __ia32_ASM_H__
#include <arch/pm.h>
#include <arch/types.h>
#include <config.h>
251,4 → 252,40
__asm__ volatile ("invlpg %0\n" :: "m" (*(__native *)addr));
}
/** Load GDTR register from memory.
*
* @param gdtr_reg Address of memory from where to load GDTR.
*/
static inline void gdtr_load(struct ptr_16_32 *gdtr_reg)
{
__asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg));
}
/** Store GDTR register to memory.
*
* @param gdtr_reg Address of memory to where to load GDTR.
*/
static inline void gdtr_store(struct ptr_16_32 *gdtr_reg)
{
__asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg));
}
/** Load IDTR register from memory.
*
* @param idtr_reg Address of memory from where to load IDTR.
*/
static inline void idtr_load(struct ptr_16_32 *idtr_reg)
{
__asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg));
}
/** Load TR from descriptor table.
*
* @param sel Selector specifying descriptor of TSS segment.
*/
static inline void tr_load(__u16 sel)
{
__asm__ volatile ("ltr %0" : : "r" (sel));
}
#endif

/kernel/trunk/arch/ia32/src/pm.c
178,8 → 178,8
*/
idtr.limit = sizeof(idt);
idtr.base = (__address) idt;
__asm__ volatile ("lgdt %0\n" : : "m" (gdtr));
__asm__ volatile ("lidt %0\n" : : "m" (idtr));
gdtr_load(&gdtr);
idtr_load(&idtr);
/*
* Each CPU has its private GDT and TSS.
213,7 → 213,7
* As of this moment, the current CPU has its own GDT pointing
* to its own TSS. We just need to load the TR register.
*/
__asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
tr_load(selector(TSS_DES));
clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */
clean_AM_flag(); /* Disable alignment check */
224,9 → 224,8
struct ptr_16_32 cpugdtr;
struct descriptor *gdt_p = (struct descriptor *) cpugdtr.base;
__asm__ volatile ("sgdt %0\n" : : "m" (cpugdtr));
gdtr_store(&cpugdtr);
gdt_setbase(&gdt_p[TLS_DES], tls);
/* Reload gdt register to update GS in CPU */
__asm__ volatile ("lgdt %0\n" : : "m" (cpugdtr));
gdtr_load(&cpugdtr);
}