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Ignore whitespace Rev 703 → Rev 704

/kernel/trunk/generic/src/mm/as.c
58,10 → 58,10
#define KAS_INDICES (1+(KAS_END_INDEX-KAS_START_INDEX))
 
/*
* Here we assume that PFN (Physical Frame Numbers) space
* Here we assume that PFN (Physical Frame Number) space
* is smaller than the width of index_t. UNALLOCATED_PFN
* can be then used to mark mappings wich were not
* allocated a physical frame.
* yet allocated a physical frame.
*/
#define UNALLOCATED_PFN ((index_t) -1)
 
141,7 → 141,8
for (i=0; i<size; i++) {
/*
* Frames will be allocated on-demand by
* as_page_fault().
* as_page_fault() or preloaded by
* as_area_load_mapping().
*/
a->mapping[i] = UNALLOCATED_PFN;
}
159,7 → 160,7
 
spinlock_unlock(&as->lock);
interrupts_restore(ipl);
 
return a;
}
 
180,6 → 181,7
 
for (i = 0; i < a->size; i++) {
ASSERT(a->mapping[i] == UNALLOCATED_PFN);
ASSERT(pfn[i] != UNALLOCATED_PFN);
a->mapping[i] = pfn[i];
}
194,7 → 196,7
*
* @param page Faulting page.
*
* @return 0 on page fault, 1 if address space operation
* @return 0 on page fault, 1 on success.
*/
int as_page_fault(__address page)
{
250,6 → 252,7
frame = frame_alloc(0, ONE_FRAME, NULL);
memsetb(frame, FRAME_SIZE, 0);
area->mapping[vpn] = frame / FRAME_SIZE;
ASSERT(area->mapping[vpn] != UNALLOCATED_PFN);
} else {
frame = area->mapping[vpn] * FRAME_SIZE;
}
/kernel/trunk/arch/mips32/src/mm/tlb.c
399,9 → 399,11
{
page_mask_t mask;
entry_lo_t lo0, lo1;
entry_hi_t hi;
entry_hi_t hi, hi_save;
int i;
 
hi_save.value = cp0_entry_hi_read();
 
printf("TLB:\n");
for (i = 0; i < TLB_ENTRY_COUNT; i++) {
cp0_index_write(i);
417,6 → 419,8
i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
}
cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all not wired TLB entries. */
424,8 → 428,10
{
ipl_t ipl;
entry_lo_t lo0, lo1;
entry_hi_t hi_save;
int i;
 
hi_save.value = cp0_entry_hi_read();
ipl = interrupts_disable();
 
for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
445,6 → 451,7
}
interrupts_restore(ipl);
cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all TLB entries belonging to specified address space.
455,11 → 462,12
{
ipl_t ipl;
entry_lo_t lo0, lo1;
entry_hi_t hi;
entry_hi_t hi, hi_save;
int i;
 
ASSERT(asid != ASID_INVALID);
 
hi_save.value = cp0_entry_hi_read();
ipl = interrupts_disable();
for (i = 0; i < TLB_ENTRY_COUNT; i++) {
483,6 → 491,7
}
interrupts_restore(ipl);
cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate TLB entry for specified page belonging to specified address space.
494,11 → 503,12
{
ipl_t ipl;
entry_lo_t lo0, lo1;
entry_hi_t hi;
entry_hi_t hi, hi_save;
tlb_index_t index;
 
ASSERT(asid != ASID_INVALID);
 
hi_save.value = cp0_entry_hi_read();
ipl = interrupts_disable();
 
hi.value = 0;
525,4 → 535,5
}
interrupts_restore(ipl);
cp0_entry_hi_write(hi_save.value);
}