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Ignore whitespace Rev 1266 → Rev 1267

/kernel/trunk/arch/ppc32/include/asm/regname.h
194,6 → 194,8
/* MSR bits */
#define msr_ir (1 << 4)
#define msr_dr (1 << 5)
#define msr_pr (1 << 14)
#define msr_ee (1 << 15)
 
/* HID0 bits */
#define hid0_ice (1 << 15)
/kernel/trunk/arch/ppc32/include/interrupt.h
29,8 → 29,7
#ifndef __ppc32_INTERRUPT_H__
#define __ppc32_INTERRUPT_H__
 
#define IRQ_COUNT 1 /* TODO */
 
#define IRQ_COUNT 1
#define IVT_ITEMS 15
#define INT_OFFSET 0
 
/kernel/trunk/arch/ppc32/include/exception.h
47,7 → 47,6
__u32 r9;
__u32 r10;
__u32 r11;
__u32 r12;
__u32 r13;
__u32 r14;
__u32 r15;
/kernel/trunk/arch/ppc32/include/byteorder.h
51,8 → 51,12
{
__address v;
__asm__ volatile ("lwbrx %0, %1, %2\n" : "=r" (v) : "i" (0) , "r" (&n));
asm volatile (
"lwbrx %0, %1, %2\n"
: "=r" (v)
: "i" (0), "r" (&n)
);
return v;
}
 
#endif
/kernel/trunk/arch/ppc32/include/cpuid.h
38,8 → 38,8
 
static inline void cpu_version(struct cpu_info *info)
{
__asm__ volatile (
"mfspr %0, 287\n"
asm volatile (
"mfpvr %0\n"
: "=r" (*info)
);
}
/kernel/trunk/arch/ppc32/include/atomic.h
33,7 → 33,7
{
long tmp;
 
asm __volatile__ (
asm volatile (
"1:\n"
"lwarx %0, 0, %2\n"
"addic %0, %0, 1\n"
41,7 → 41,8
"bne- 1b"
: "=&r" (tmp), "=m" (val->count)
: "r" (&val->count), "m" (val->count)
: "cc");
: "cc"
);
}
 
static inline void atomic_dec(atomic_t *val)
48,7 → 49,7
{
long tmp;
 
asm __volatile__(
asm volatile (
"1:\n"
"lwarx %0, 0, %2\n"
"addic %0, %0, -1\n"
56,7 → 57,8
"bne- 1b"
: "=&r" (tmp), "=m" (val->count)
: "r" (&val->count), "m" (val->count)
: "cc");
: "cc"
);
}
 
static inline long atomic_postinc(atomic_t *val)
/kernel/trunk/arch/ppc32/include/asm.h
40,10 → 40,10
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_enable(void) {
ipl_t v;
ipl_t v = 0;
ipl_t tmp;
__asm__ volatile (
asm volatile (
"mfmsr %0\n"
"mfmsr %1\n"
"ori %1, %1, 1 << 15\n"
64,7 → 64,7
ipl_t v;
ipl_t tmp;
__asm__ volatile (
asm volatile (
"mfmsr %0\n"
"mfmsr %1\n"
"rlwinm %1, %1, 0, 17, 15\n"
83,7 → 83,7
static inline void interrupts_restore(ipl_t ipl) {
ipl_t tmp;
__asm__ volatile (
asm volatile (
"mfmsr %1\n"
"rlwimi %0, %1, 0, 17, 15\n"
"cmpw 0, %0, %1\n"
103,7 → 103,8
*/
static inline ipl_t interrupts_read(void) {
ipl_t v;
__asm__ volatile (
asm volatile (
"mfmsr %0\n"
: "=r" (v)
);
120,8 → 121,11
{
__address v;
__asm__ volatile ("and %0, %%sp, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
asm volatile (
"and %0, %%sp, %1\n"
: "=r" (v)
: "r" (~(STACK_SIZE - 1))
);
return v;
}
 
/kernel/trunk/arch/ppc32/include/barrier.h
29,11 → 29,11
#ifndef __ppc32_BARRIER_H__
#define __ppc32_BARRIER_H__
 
#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory")
#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory")
#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory")
#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory")
 
#define memory_barrier() __asm__ volatile ("sync" ::: "memory")
#define read_barrier() __asm__ volatile ("sync" ::: "memory")
#define write_barrier() __asm__ volatile ("eieio" ::: "memory")
#define memory_barrier() asm volatile ("sync" ::: "memory")
#define read_barrier() asm volatile ("sync" ::: "memory")
#define write_barrier() asm volatile ("eieio" ::: "memory")
 
#endif
/kernel/trunk/arch/ppc32/src/exception.S
32,11 → 32,35
.section K_UNMAPPED_TEXT_START, "ax"
 
.macro CONTEXT_STORE
mtspr sprg1, sp
subis sp, sp, 0x8000
# save SP in SPRG1
# save R12 in SPRG2, backup CR in R12
 
mtsprg1 sp
mtsprg2 r12
mfcr r12
subi sp, sp, 144
# check whether SP is in kernel
andis. sp, sp, 0x8000
bne 1f
# stack is in user-space
mfsprg0 sp
b 2f
1:
# stack is in kernel
mfsprg1 sp
subis sp, sp, 0x8000
2:
subi sp, sp, 140
stw r0, 0(sp)
stw r2, 4(sp)
stw r3, 8(sp)
48,44 → 72,42
stw r9, 32(sp)
stw r10, 36(sp)
stw r11, 40(sp)
stw r12, 44(sp)
stw r13, 48(sp)
stw r14, 52(sp)
stw r15, 56(sp)
stw r16, 60(sp)
stw r17, 64(sp)
stw r18, 68(sp)
stw r19, 72(sp)
stw r20, 76(sp)
stw r21, 80(sp)
stw r22, 84(sp)
stw r23, 88(sp)
stw r24, 92(sp)
stw r25, 96(sp)
stw r26, 100(sp)
stw r27, 104(sp)
stw r28, 108(sp)
stw r29, 112(sp)
stw r30, 116(sp)
stw r31, 120(sp)
stw r13, 44(sp)
stw r14, 48(sp)
stw r15, 52(sp)
stw r16, 56(sp)
stw r17, 60(sp)
stw r18, 64(sp)
stw r19, 68(sp)
stw r20, 72(sp)
stw r21, 76(sp)
stw r22, 80(sp)
stw r23, 84(sp)
stw r24, 88(sp)
stw r25, 92(sp)
stw r26, 96(sp)
stw r27, 100(sp)
stw r28, 104(sp)
stw r29, 108(sp)
stw r30, 112(sp)
stw r31, 116(sp)
mfspr r3, srr0
mfsrr0 r3
stw r3, 120(sp)
mfsrr1 r3
stw r3, 124(sp)
mfspr r3, srr1
mflr r3
stw r3, 128(sp)
mflr r3
stw r3, 132(sp)
stw r12, 132(sp)
mfcr r3
mfctr r3
stw r3, 136(sp)
mfctr r3
mfxer r3
stw r3, 140(sp)
mfxer r3
stw r3, 144(sp)
.endm
 
.org 0x100
102,14 → 124,14
.global exc_data_storage
exc_data_storage:
CONTEXT_STORE
 
lis r3, pht_refill@ha
addi r3, r3, pht_refill@l
mtspr srr0, r3
mtsrr0 r3
mfmsr r3
ori r3, r3, (msr_ir | msr_dr)@l
mtspr srr1, r3
mtsrr1 r3
lis r3, iret@ha
addi r3, r3, iret@l
116,18 → 138,30
mtlr r3
addis sp, sp, 0x8000
mr r3, sp
rfi
 
.org 0x400
.global exc_instruction_storage
exc_instruction_storage:
b exc_instruction_storage
CONTEXT_STORE
lis r3, pht_refill@ha
addi r3, r3, pht_refill@l
mtsrr0 r3
mfmsr r3
ori r3, r3, (msr_ir | msr_dr)@l
mtsrr1 r3
lis r3, iret@ha
addi r3, r3, iret@l
mtlr r3
addis sp, sp, 0x8000
mr r3, sp
rfi
 
.org 0x480
.global exc_instruction_segment
exc_instruction_segment:
b exc_instruction_segment
 
.org 0x500
.global exc_external
exc_external:
155,11 → 189,11
 
lis r3, exc_dispatch@ha
addi r3, r3, exc_dispatch@l
mtspr srr0, r3
mtsrr0 r3
mfmsr r3
ori r3, r3, (msr_ir | msr_dr)@l
mtspr srr1, r3
mtsrr1 r3
lis r3, iret@ha
addi r3, r3, iret@l
167,6 → 201,7
addis sp, sp, 0x8000
li r3, 10
mr r4, sp
rfi
 
.org 0xa00
/kernel/trunk/arch/ppc32/src/asm.S
39,7 → 39,9
 
# r3 = uspace_uarg
# r4 = stack
# r5 = entry
# r5 = entry
# disable interrupts
 
mfmsr r31
rlwinm r31, r31, 0, 17, 15
51,8 → 53,8
# set problem state, enable interrupts
ori r31, r31, 1 << 14
ori r31, r31, 1 << 15
ori r31, r31, msr_pr
ori r31, r31, msr_ee
mtsrr1 r31
# set stack
64,24 → 66,6
rfi
 
iret:
lwz r3, 144(sp)
mtxer r3
lwz r3, 140(sp)
mtctr r3
lwz r3, 136(sp)
mtcr r3
lwz r3, 132(sp)
mtlr r3
lwz r3, 128(sp)
mtspr srr1, r3
lwz r3, 124(sp)
mtspr srr0, r3
lwz r0, 0(sp)
lwz r2, 4(sp)
lwz r3, 8(sp)
93,29 → 77,47
lwz r9, 32(sp)
lwz r10, 36(sp)
lwz r11, 40(sp)
lwz r12, 44(sp)
lwz r13, 48(sp)
lwz r14, 52(sp)
lwz r15, 56(sp)
lwz r16, 60(sp)
lwz r17, 64(sp)
lwz r18, 68(sp)
lwz r19, 72(sp)
lwz r20, 76(sp)
lwz r21, 80(sp)
lwz r22, 84(sp)
lwz r23, 88(sp)
lwz r24, 92(sp)
lwz r25, 96(sp)
lwz r26, 100(sp)
lwz r27, 104(sp)
lwz r28, 108(sp)
lwz r29, 112(sp)
lwz r30, 116(sp)
lwz r31, 120(sp)
lwz r13, 44(sp)
lwz r14, 48(sp)
lwz r15, 52(sp)
lwz r16, 56(sp)
lwz r17, 60(sp)
lwz r18, 64(sp)
lwz r19, 68(sp)
lwz r20, 72(sp)
lwz r21, 76(sp)
lwz r22, 80(sp)
lwz r23, 84(sp)
lwz r24, 88(sp)
lwz r25, 92(sp)
lwz r26, 96(sp)
lwz r27, 100(sp)
lwz r28, 104(sp)
lwz r29, 108(sp)
lwz r30, 112(sp)
lwz r31, 116(sp)
mfspr sp, sprg1
lwz r12, 120(sp)
mtsrr0 r12
lwz r12, 124(sp)
mtsrr1 r12
lwz r12, 128(sp)
mtlr r12
lwz r12, 132(sp)
mtcr r12
lwz r12, 136(sp)
mtctr r12
lwz r12, 140(sp)
mtxer r12
 
mfsprg1 sp
mfsprg2 r12
rfi
memsetb:
/kernel/trunk/arch/ppc32/src/boot/boot.S
34,18 → 34,21
.global kernel_image_start
kernel_image_start:
 
# load temporary stack
# load temporal kernel stack
lis sp, end_stack@ha
addi sp, sp, end_stack@l
lis sp, kernel_stack@ha
addi sp, sp, kernel_stack@l
# set kernel stack for interrupt handling
mr r31, sp
subis r31, r31, 0x8000
mtsprg0 r31
# r3 contains physical address of bootinfo_t
# r4 contains size of bootinfo_t
lis r31, 0x80000000@ha
addi r31, r31, 0x80000000@l
add r3, r3, r31
addis r3, r3, 0x8000
 
lis r31, bootinfo@ha
addi r31, r31, bootinfo@l # r31 = bootinfo
72,5 → 75,7
 
.section K_DATA_START, "aw", @progbits
 
.align 12
kernel_stack_bottom:
.space TEMP_STACK_SIZE
end_stack:
kernel_stack:
/kernel/trunk/arch/ppc32/src/proc/scheduler.c
27,13 → 27,11
*/
 
#include <arch/mm/page.h>
#include <arch/boot/boot.h>
#include <proc/scheduler.h>
#include <proc/thread.h>
#include <arch.h>
 
__address supervisor_sp;
__address supervisor_sp_physical;
 
/** Perform ppc32 specific tasks needed before the new task is run. */
void before_task_runs_arch(void)
{
42,8 → 40,11
/** Perform ppc32 specific tasks needed before the new thread is scheduled. */
void before_thread_runs_arch(void)
{
supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA];
supervisor_sp_physical = KA2PA(supervisor_sp_physical);
asm volatile (
"mtsprg0 %0\n"
:
: "r" (KA2PA(&THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA]))
);
}
 
void after_thread_ran_arch(void)
/kernel/trunk/arch/ppc32/src/interrupt.c
31,9 → 31,9
#include <arch/types.h>
#include <arch.h>
#include <time/clock.h>
#include <print.h>
#include <ipc/sysipc.h>
 
 
void start_decrementer(void)
{
asm volatile (