WebSVN – HelenOS-historic – Path Comparison – / – /kernel/ Rev 1118 and /kernel/ Rev 1119

Ignore whitespace Rev 1118 → Rev 1119

 /kernel/trunk/arch/amd64/src/userspace.c
 ,7 → 46,7
     ipl = interrupts_disable();
     /* Clear CF,PF,AF,ZF,SF,DF,OF */
-    ipl &= ~ (0xbc4);
+    ipl &= ~(0xcd4);
     __asm__ volatile (""
               "pushq %0\n"

 /kernel/trunk/arch/mips32/src/exception.c
 ,6 → 83,18
     panic("unhandled exception %s\n", exctable[n]);
 }
+static void reserved_instr_exception(int n, istate_t *istate)
+{
+    if (*((__u32 *)istate->epc) == 0x7c03e83b) {
+        ASSERT(THREAD);
+        istate->epc += 4;
+        istate->v1 = istate->k1;
+    } else {
+        print_regdump(istate);
+        panic("reserved instruction");
+    }
+}
 static void breakpoint_exception(int n, istate_t *istate)
 {
 #ifdef CONFIG_DEBUG
 ,6 → 154,7
     for (i=0;i < IVT_ITEMS; i++)
         exc_register(i, "undef", (iroutine) unhandled_exception);
     exc_register(EXC_Bp, "bkpoint", (iroutine) breakpoint_exception);
+    exc_register(EXC_RI, "resinstr", (iroutine) reserved_instr_exception);
     exc_register(EXC_Mod, "tlb_mod", (iroutine) tlbmod_exception);
     exc_register(EXC_TLBL, "tlbinvl", (iroutine) tlbinv_exception);
     exc_register(EXC_TLBS, "tlbinvl", (iroutine) tlbinv_exception);

 /kernel/trunk/arch/ia32/src/ia32.c
 ,11 → 111,8
 /** Set Thread-local-storeage pointer
  *
- * TLS pointer is set in FS register. Unfortunately the 64-bit
- * part can be set only in CPL0 mode.
- *
- * The specs says, that on %fs:0 there is stored contents of %fs register,
- * we need not to go to CPL0 to read it.
+ * TLS pointer is set in GS register. That means, the GS contains
+ * selector, and the descriptor->base is the correct address.
  */
 __native sys_tls_set(__native addr)
 {