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Ignore whitespace Rev 324 → Rev 326

/SPARTAN/trunk/arch/mips/src/exception.c
51,6 → 51,9
cpu_priority_high();
cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
cp0_status_um_bit));
/* Save pstate so that the threads can access it */
if (THREAD)
THREAD->pstate = pstate;
 
/* decode exception number and process the exception */
switch (excno = (cp0_cause_read() >> 2) & 0x1f) {
85,7 → 88,11
panic("unhandled Reserved Instruction Exception\n");
break;
case EXC_CpU:
#ifdef FPU_LAZY
scheduler_fpu_lazy_request();
#else
panic("unhandled Coprocessor Unusable Exception\n");
#endif
break;
case EXC_Ov:
panic("unhandled Arithmetic Overflow Exception\n");
110,4 → 117,8
}
pstate->epc += epc_shift;
/* Probable not needed, but just for sure that nobody
* will continue accessing it */
if (THREAD)
THREAD->pstate = NULL;
}
/SPARTAN/trunk/arch/mips/src/fpu_context.c
28,13 → 28,28
*/
 
#include <fpu_context.h>
#include <arch.h>
#include <arch/cp0.h>
 
void fpu_context_save(fpu_context_t *fctx)
void fpu_disable(void)
{
#ifdef HAVE_FPU
cp0_status_write(cp0_status_read() & ~cp0_status_fpu_bit);
if (THREAD && THREAD->pstate)
THREAD->pstate->status &= ~cp0_status_fpu_bit;
#endif
}
 
void fpu_enable(void)
{
#ifdef HAVE_FPU
cp0_status_write(cp0_status_read() | cp0_status_fpu_bit);
if (THREAD && THREAD->pstate)
THREAD->pstate->status |= cp0_status_fpu_bit;
#endif
}
 
 
void fpu_context_restore(fpu_context_t *fctx)
void fpu_init(void)
{
/* TODO: Zero all registers */
}
 
/SPARTAN/trunk/arch/mips/src/asm.S
26,6 → 26,8
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/asm/regname.h>
.text
 
.macro cp0_read reg
115,30 → 117,6
cp0_prid_read: cp0_read $15
 
 
.global tlbp
tlbp:
tlbp
j $31
nop
 
.global tlbr
tlbr:
tlbr
j $31
nop
 
.global tlbwi
tlbwi:
tlbwi
j $31
nop
 
.global tlbwr
tlbwr:
tlbwr
j $31
nop
 
.global cpu_halt
cpu_halt:
j cpu_halt
155,6 → 133,169
j _memcpy
nop
 
.macro fpu_gp_save reg ctx
mfc1 $t0,$\reg
sw $t0, \reg*4(\ctx)
.endm
 
.macro fpu_gp_restore reg ctx
lw $t0, \reg*4(\ctx)
mtc1 $t0,$\reg
.endm
 
.macro fpu_ct_save reg ctx
cfc1 $t0,$1
sw $t0, (\reg+32)*4(\ctx)
.endm
 
.macro fpu_ct_restore reg ctx
lw $t0, (\reg+32)*4(\ctx)
ctc1 $t0,$\reg
.endm
 
 
.global fpu_context_save
fpu_context_save:
#ifdef HAVE_FPU
fpu_gp_save 0,$a0
fpu_gp_save 1,$a0
fpu_gp_save 2,$a0
fpu_gp_save 3,$a0
fpu_gp_save 4,$a0
fpu_gp_save 5,$a0
fpu_gp_save 6,$a0
fpu_gp_save 7,$a0
fpu_gp_save 8,$a0
fpu_gp_save 9,$a0
fpu_gp_save 10,$a0
fpu_gp_save 11,$a0
fpu_gp_save 12,$a0
fpu_gp_save 13,$a0
fpu_gp_save 14,$a0
fpu_gp_save 15,$a0
fpu_gp_save 16,$a0
fpu_gp_save 17,$a0
fpu_gp_save 18,$a0
fpu_gp_save 19,$a0
fpu_gp_save 20,$a0
fpu_gp_save 21,$a0
fpu_gp_save 22,$a0
fpu_gp_save 23,$a0
fpu_gp_save 24,$a0
fpu_gp_save 25,$a0
fpu_gp_save 26,$a0
fpu_gp_save 27,$a0
fpu_gp_save 28,$a0
fpu_gp_save 29,$a0
fpu_gp_save 30,$a0
fpu_gp_save 31,$a0
 
fpu_ct_save 1,$a0
fpu_ct_save 2,$a0
fpu_ct_save 3,$a0
fpu_ct_save 4,$a0
fpu_ct_save 5,$a0
fpu_ct_save 6,$a0
fpu_ct_save 7,$a0
fpu_ct_save 8,$a0
fpu_ct_save 9,$a0
fpu_ct_save 10,$a0
fpu_ct_save 11,$a0
fpu_ct_save 12,$a0
fpu_ct_save 13,$a0
fpu_ct_save 14,$a0
fpu_ct_save 15,$a0
fpu_ct_save 16,$a0
fpu_ct_save 17,$a0
fpu_ct_save 18,$a0
fpu_ct_save 19,$a0
fpu_ct_save 20,$a0
fpu_ct_save 21,$a0
fpu_ct_save 22,$a0
fpu_ct_save 23,$a0
fpu_ct_save 24,$a0
fpu_ct_save 25,$a0
fpu_ct_save 26,$a0
fpu_ct_save 27,$a0
fpu_ct_save 28,$a0
fpu_ct_save 29,$a0
fpu_ct_save 30,$a0
fpu_ct_save 31,$a0
#endif
j $ra
nop
 
.global fpu_context_restore
fpu_context_restore:
#ifdef HAVE_FPU
fpu_gp_restore 0,$a0
fpu_gp_restore 1,$a0
fpu_gp_restore 2,$a0
fpu_gp_restore 3,$a0
fpu_gp_restore 4,$a0
fpu_gp_restore 5,$a0
fpu_gp_restore 6,$a0
fpu_gp_restore 7,$a0
fpu_gp_restore 8,$a0
fpu_gp_restore 9,$a0
fpu_gp_restore 10,$a0
fpu_gp_restore 11,$a0
fpu_gp_restore 12,$a0
fpu_gp_restore 13,$a0
fpu_gp_restore 14,$a0
fpu_gp_restore 15,$a0
fpu_gp_restore 16,$a0
fpu_gp_restore 17,$a0
fpu_gp_restore 18,$a0
fpu_gp_restore 19,$a0
fpu_gp_restore 20,$a0
fpu_gp_restore 21,$a0
fpu_gp_restore 22,$a0
fpu_gp_restore 23,$a0
fpu_gp_restore 24,$a0
fpu_gp_restore 25,$a0
fpu_gp_restore 26,$a0
fpu_gp_restore 27,$a0
fpu_gp_restore 28,$a0
fpu_gp_restore 29,$a0
fpu_gp_restore 30,$a0
fpu_gp_restore 31,$a0
 
fpu_ct_restore 1,$a0
fpu_ct_restore 2,$a0
fpu_ct_restore 3,$a0
fpu_ct_restore 4,$a0
fpu_ct_restore 5,$a0
fpu_ct_restore 6,$a0
fpu_ct_restore 7,$a0
fpu_ct_restore 8,$a0
fpu_ct_restore 9,$a0
fpu_ct_restore 10,$a0
fpu_ct_restore 11,$a0
fpu_ct_restore 12,$a0
fpu_ct_restore 13,$a0
fpu_ct_restore 14,$a0
fpu_ct_restore 15,$a0
fpu_ct_restore 16,$a0
fpu_ct_restore 17,$a0
fpu_ct_restore 18,$a0
fpu_ct_restore 19,$a0
fpu_ct_restore 20,$a0
fpu_ct_restore 21,$a0
fpu_ct_restore 22,$a0
fpu_ct_restore 23,$a0
fpu_ct_restore 24,$a0
fpu_ct_restore 25,$a0
fpu_ct_restore 26,$a0
fpu_ct_restore 27,$a0
fpu_ct_restore 28,$a0
fpu_ct_restore 29,$a0
fpu_ct_restore 30,$a0
fpu_ct_restore 31,$a0
#endif
j $ra
nop
# THIS IS USERSPACE CODE
.global utext
utext:
/SPARTAN/trunk/arch/mips/src/console.c
31,8 → 31,6
#include <arch/cp0.h>
#include <arch/console.h>
 
static void (*putchar_func)(const char ch) = NULL;
 
static void cons_putchar(const char ch)
{
*((char *) VIDEORAM) = ch;
52,6 → 50,8
*(SERIAL_PORT_BASE) = ch;
}
 
static void (*putchar_func)(const char ch) = cons_putchar;
 
void console_init(void)
{
/* The LSR on the start usually contains this value */
/SPARTAN/trunk/arch/mips/src/mips.c
34,9 → 34,27
#include <mm/vm.h>
#include <userspace.h>
#include <arch/console.h>
#include <memstr.h>
 
/* Size of the code jumping to the exception handler code
* - J+NOP
*/
#define EXCEPTION_JUMP_SIZE 8
 
#define TLB_EXC ((char *) 0x80000000)
#define NORM_EXC ((char *) 0x80000180)
#define CACHE_EXC ((char *) 0x80000100)
 
#include <arch/debug.h>
 
void arch_pre_mm_init(void)
{
/* Copy the exception vectors to the right places */
memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE);
memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE);
memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
 
 
/*
* Switch to BEV normal level so that exception vectors point to the kernel.
* Clear the error level.
/SPARTAN/trunk/arch/mips/src/mm/frame.c
31,4 → 31,6
 
void frame_arch_init(void)
{
/* Disable first megabyte (God knows why) */
frame_region_not_free(0, 1024*1024);
}
/SPARTAN/trunk/arch/mips/src/panic.S
32,11 → 32,12
.set noreorder
.set nomacro
 
#include <arch/asm/regname.h>
.global panic_printf
 
/* From printf return directly to halt() */
panic_printf:
jal printf
nop
j cpu_halt
nop
 
lui $ra, %hi(halt)
j printf
ori $ra, %lo(halt)
/SPARTAN/trunk/arch/mips/src/dummy.S
32,15 → 32,9
.global calibrate_delay_loop
.global asm_delay_loop
.global dummy
.global fpu_enable
.global fpu_disable
.global fpu_init
calibrate_delay_loop:
asm_delay_loop:
fpu_enable:
fpu_disable:
fpu_init:
 
dummy:
j $31
/SPARTAN/trunk/arch/mips/src/start.S
153,26 → 153,6
.endm
.org 0x0
tlb_refill_entry:
j tlb_refill_handler
nop
 
.org 0x100
cache_error_entry:
j cache_error_handler
nop
 
.org 0x180
norm_exception:
j exception_handler
nop
 
.org 0x200
iv_exception:
j exception_handler
nop
 
.org KA2PA(KERNEL_STARTUP_ADDRESS)
kernel_image_start:
/* Load temporary stack */
lui $sp, %hi(end_stack)
186,10 → 166,23
 
 
.space TEMP_STACK_SIZE
end_stack:
end_stack:
 
tlb_refill_entry:
j tlb_refill_handler
nop
 
cache_error_entry:
j cache_error_handler
nop
 
exception_entry:
j exception_handler
nop
 
exception_handler:
exception_entry:
KERNEL_STACK_TO_K0
sub $k0, REGISTER_SPACE
REGISTERS_STORE $k0