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Ignore whitespace Rev 402 → Rev 403

/SPARTAN/trunk/arch/ia64/include/context.h
49,8 → 49,8
 
#define context_set(c, _pc, stack, size) \
(c)->pc = (__address) _pc; \
(c)->bsp = ((__address) stack) + (ALIGN(sizeof(the_t), STACK_ALIGNMENT)); \
(c)->sp = ((__address) stack) + (size) - SP_DELTA;
(c)->bsp = ((__address) stack) + ALIGN(sizeof(the_t), STACK_ALIGNMENT); \
(c)->sp = ((__address) stack) + ALIGN((size) - SP_DELTA, STACK_ALIGNMENT);
 
/*
* Only save registers that must be preserved across
/SPARTAN/trunk/arch/mips32/include/types.h
49,6 → 49,6
 
typedef __u32 __native;
 
typedef struct pte pte_t;
typedef union pte pte_t;
 
#endif
/SPARTAN/trunk/arch/mips32/include/mm/page.h
62,15 → 62,15
#define GET_PTL0_ADDRESS_ARCH() (PTL0)
#define SET_PTL0_ADDRESS_ARCH(ptl0) (PTL0 = (pte_t *)(ptl0))
 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].pfn<<12)
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].lo.pfn<<12)
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *)(ptl3))[(i)].pfn<<12)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *)(ptl3))[(i)].lo.pfn<<12)
 
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].pfn = (a)>>12)
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].lo.pfn = (a)>>12)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].pfn = (a)>>12)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].lo.pfn = (a)>>12)
 
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
94,8 → 94,8
pte_t *p = &pt[i];
return (
((p->c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) |
((!p->v)<<PAGE_PRESENT_SHIFT) |
((p->lo.c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) |
((!p->lo.v)<<PAGE_PRESENT_SHIFT) |
(1<<PAGE_USER_SHIFT) |
(1<<PAGE_READ_SHIFT) |
((p->w)<<PAGE_WRITE_SHIFT) |
108,8 → 108,8
{
pte_t *p = &pt[i];
p->c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
p->v = !(flags & PAGE_NOT_PRESENT);
p->lo.c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
p->lo.v = !(flags & PAGE_NOT_PRESENT);
p->w = (flags & PAGE_WRITE) != 0;
}
 
/SPARTAN/trunk/arch/mips32/include/mm/tlb.h
30,6 → 30,7
#define __mips32_TLB_H__
 
#include <arch/exception.h>
#include <typedefs.h>
 
#define TLB_SIZE 48
 
41,6 → 42,11
#define PAGE_UNCACHED 2
#define PAGE_CACHEABLE_EXC_WRITE 5
 
typedef union entry_lo entry_lo_t;
typedef union entry_hi entry_hi_t;
typedef union page_mask page_mask_t;
typedef union index tlb_index_t;
 
union entry_lo {
struct {
unsigned g : 1; /* global bit */
53,15 → 59,14
__u32 value;
};
 
struct pte {
unsigned g : 1; /* global bit */
unsigned v : 1; /* valid bit */
unsigned d : 1; /* dirty/write-protect bit */
unsigned c : 3; /* cache coherency attribute */
unsigned pfn : 24; /* frame number */
unsigned w : 1; /* writable */
unsigned a : 1; /* accessed */
} __attribute__ ((packed));
union pte {
entry_lo_t lo;
struct {
unsigned : 30;
unsigned w : 1; /* writable */
unsigned a : 1; /* accessed */
} __attribute__ ((packed));
};
 
union entry_hi {
struct {
90,11 → 95,6
__u32 value;
};
 
typedef union entry_lo entry_lo_t;
typedef union entry_hi entry_hi_t;
typedef union page_mask page_mask_t;
typedef union index tlb_index_t;
 
/** Probe TLB for Matching Entry
*
* Probe TLB for Matching Entry.
/SPARTAN/trunk/arch/mips32/src/mm/tlb.c
104,7 → 104,7
pte->a = 1;
 
prepare_entry_hi(&hi, VM->asid, badvaddr);
prepare_entry_lo(&lo, pte->g, pte->v, pte->d, pte->c, pte->pfn);
prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
 
/*
* New entry is to be inserted into TLB
177,7 → 177,7
*/
pte->a = 1;
 
prepare_entry_lo(&lo, pte->g, pte->v, pte->d, pte->c, pte->pfn);
prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
 
/*
* The entry is to be updated in TLB.
250,9 → 250,9
* Record access and write to PTE.
*/
pte->a = 1;
pte->d = 1;
pte->lo.d = 1;
 
prepare_entry_lo(&lo, pte->g, pte->v, pte->w, pte->c, pte->pfn);
prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn);
 
/*
* The entry is to be updated in TLB.
375,7 → 375,7
/*
* Handler cannot succeed if the mapping is marked as invalid.
*/
if (!pte->v) {
if (!pte->lo.v) {
printf("Invalid mapping.\n");
return NULL;
}