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Ignore whitespace Rev 992 → Rev 993

/kernel/trunk/arch/ia64/include/interrupt.h
71,7 → 71,7
__u64 in2;
__u64 in3;
__u64 in4;
} __attribute__ ((packed));
};
 
extern void *ivt;
 
/kernel/trunk/arch/ia64/include/context.h
97,6 → 97,6
__u64 pr;
ipl_t ipl;
} __attribute__ ((packed));
};
 
#endif
/kernel/trunk/arch/ia64/src/fpu_context.c
28,8 → 28,10
*/
 
#include <fpu_context.h>
#include <print.h>
 
void fpu_context_save(fpu_context_t *fctx){
return;
asm volatile(
"stf.spill [%2]=f2,0x80\n"
"stf.spill [%3]=f3,0x80\n"
186,7 → 188,7
 
void fpu_context_restore(fpu_context_t *fctx)
{
 
return;
asm volatile(
"ldf.fill f2=[%2],0x80\n"
"ldf.fill f3=[%3],0x80\n"
/kernel/trunk/arch/ia64/src/asm.S
60,7 → 60,7
.global switch_to_userspace
switch_to_userspace:
alloc loc0 = ar.pfs, 5, 3, 0, 0
rsm (PSR_IC_MASK | PSR_I_MASK) /* disable interruption collection and interrupts */
rsm (PSR_IC_MASK | PSR_I_MASK) /* disable interruption collection and interrupts */
srlz.d ;;
srlz.i ;;
/kernel/trunk/arch/ia64/src/ivt.S
315,7 → 315,7
mov loc45 = r30
mov loc46 = r31
 
/*preserve Floating point status register*/
/* preserve Floating point status register */
mov loc47 = ar.fpsr
/* 9. skipped (will not enable interrupts) */
375,8 → 375,7
mov r30 = loc45
mov r31 = loc46
 
/*restore Floating point status register*/
/* restore Floating point status register */
mov ar.fpsr = loc47
/* 14. restore branch and application registers */
/kernel/trunk/arch/ia64/src/proc/scheduler.c
62,8 → 62,7
"mov r23 = %1\n"
"bsw.1\n"
:
: /*"r" (((__address) THREAD->kstack) + ALIGN_UP(sizeof(the_t), REGISTER_STACK_ALIGNMENT)),*/
"r" (&THREAD->kstack[THREAD_STACK_SIZE]),
: "r" (&THREAD->kstack[THREAD_STACK_SIZE]),
"r" (&THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA])
);
}
/kernel/trunk/arch/ia64/src/ia64.c
77,6 → 77,7
psr.i = true; /* start with interrupts enabled */
psr.ic = true;
psr.ri = 0; /* start with instruction #0 */
psr.bn = 1; /* start in bank 0 */
 
__asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
rsc.loadrs = 0;
/kernel/trunk/arch/ia64/src/mm/tlb.c
42,42 → 42,39
#include <arch/asm.h>
#include <typedefs.h>
#include <panic.h>
#include <print.h>
#include <arch.h>
 
 
 
/** Invalidate all TLB entries. */
void tlb_invalidate_all(void)
{
ipl_t ipl;
__address adr;
__u32 count1,count2,stride1,stride2;
__u32 count1, count2, stride1, stride2;
int i,j;
adr=PAL_PTCE_INFO_BASE();
count1=PAL_PTCE_INFO_COUNT1();
count2=PAL_PTCE_INFO_COUNT2();
stride1=PAL_PTCE_INFO_STRIDE1();
stride2=PAL_PTCE_INFO_STRIDE2();
adr = PAL_PTCE_INFO_BASE();
count1 = PAL_PTCE_INFO_COUNT1();
count2 = PAL_PTCE_INFO_COUNT2();
stride1 = PAL_PTCE_INFO_STRIDE1();
stride2 = PAL_PTCE_INFO_STRIDE2();
interrupts_disable();
ipl = interrupts_disable();
 
for(i=0;i<count1;i++)
{
for(j=0;j<count2;j++)
{
asm volatile
(
"ptc.e %0;;"
for(i = 0; i < count1; i++) {
for(j = 0; j < count2; j++) {
__asm__ volatile (
"ptc.e %0 ;;"
:
:"r" (adr)
: "r" (adr)
);
adr+=stride2;
adr += stride2;
}
adr+=stride1;
adr += stride1;
}
 
interrupts_enable();
interrupts_restore(ipl);
 
srlz_d();
srlz_i();
89,7 → 86,6
*/
void tlb_invalidate_asid(asid_t asid)
{
/* TODO */
tlb_invalidate_all();
}
 
96,15 → 92,13
 
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
 
 
region_register rr;
bool restore_rr = false;
int b=0;
int c=cnt;
int b = 0;
int c = cnt;
 
__address va;
va=page;
va = page;
 
rr.word = rr_read(VA2VRN(va));
if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
121,95 → 115,73
srlz_i();
}
while(c>>=1) b++;
b>>=1;
while(c >>= 1)
b++;
b >>= 1;
__u64 ps;
switch(b)
{
switch (b) {
case 0: /*cnt 1-3*/
{
ps=PAGE_WIDTH;
ps = PAGE_WIDTH;
break;
}
case 1: /*cnt 4-15*/
{
/*cnt=((cnt-1)/4)+1;*/
ps=PAGE_WIDTH+2;
va&=~((1<<ps)-1);
ps = PAGE_WIDTH+2;
va &= ~((1<<ps)-1);
break;
}
case 2: /*cnt 16-63*/
{
/*cnt=((cnt-1)/16)+1;*/
ps=PAGE_WIDTH+4;
va&=~((1<<ps)-1);
ps = PAGE_WIDTH+4;
va &= ~((1<<ps)-1);
break;
}
case 3: /*cnt 64-255*/
{
/*cnt=((cnt-1)/64)+1;*/
ps=PAGE_WIDTH+6;
va&=~((1<<ps)-1);
ps = PAGE_WIDTH+6;
va &= ~((1<<ps)-1);
break;
}
case 4: /*cnt 256-1023*/
{
/*cnt=((cnt-1)/256)+1;*/
ps=PAGE_WIDTH+8;
va&=~((1<<ps)-1);
ps = PAGE_WIDTH+8;
va &= ~((1<<ps)-1);
break;
}
case 5: /*cnt 1024-4095*/
{
/*cnt=((cnt-1)/1024)+1;*/
ps=PAGE_WIDTH+10;
va&=~((1<<ps)-1);
ps = PAGE_WIDTH+10;
va &= ~((1<<ps)-1);
break;
}
case 6: /*cnt 4096-16383*/
{
/*cnt=((cnt-1)/4096)+1;*/
ps=PAGE_WIDTH+12;
va&=~((1<<ps)-1);
ps = PAGE_WIDTH+12;
va &= ~((1<<ps)-1);
break;
}
case 7: /*cnt 16384-65535*/
case 8: /*cnt 65536-(256K-1)*/
{
/*cnt=((cnt-1)/16384)+1;*/
ps=PAGE_WIDTH+14;
va&=~((1<<ps)-1);
ps = PAGE_WIDTH+14;
va &= ~((1<<ps)-1);
break;
}
default:
{
/*cnt=((cnt-1)/(16384*16))+1;*/
ps=PAGE_WIDTH+18;
va&=~((1<<ps)-1);
break;
}
}
/*cnt+=(page!=va);*/
for(;va<(page+cnt*(PAGE_SIZE));va+=(1<<ps)) {
__asm__ volatile
(
for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps)) {
__asm__ volatile (
"ptc.l %0,%1;;"
:
: "r"(va), "r"(ps<<2)
: "r" (va), "r" (ps<<2)
);
}
srlz_d();
srlz_i();
if (restore_rr) {
rr_write(VA2VRN(va), rr.word);
srlz_d();
srlz_i();
}
 
 
}
 
 
506,7 → 478,7
* Forward the page fault to address space page fault handler.
*/
if (!as_page_fault(va)) {
panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid);
panic("%s: va=%P, rid=%d, iip=%P\n", __FUNCTION__, va, rid, istate->cr_iip);
}
}
}
612,7 → 584,7
dtc_pte_copy(t);
} else {
if (!as_page_fault(va)) {
panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid);
panic("%s: va=%P, rid=%d\n", __FUNCTION__, va, rr.map.rid);
}
}
}
/kernel/trunk/arch/ia64/src/start.S
92,7 → 92,6
* Now we are paging.
*/
 
 
# switch to register bank 1
bsw.1