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Ignore whitespace Rev 649 → Rev 650

/kernel/trunk/generic/include/debug.h
50,7 → 50,7
*
*/
#ifdef CONFIG_DEBUG
# define ASSERT(expr) if (!(expr)) { panic("assertion failed (%s)", #expr); }
# define ASSERT(expr) if (!(expr)) { panic("assertion failed (%s), caller=%P\n", #expr, CALLER); }
#else
# define ASSERT(expr)
#endif
/kernel/trunk/generic/src/proc/scheduler.c
294,7 → 294,8
spinlock_unlock(&threads_lock);
 
spinlock_lock(&CPU->lock);
if(CPU->fpu_owner==THREAD) CPU->fpu_owner=NULL;
if(CPU->fpu_owner==THREAD)
CPU->fpu_owner=NULL;
spinlock_unlock(&CPU->lock);
 
free(THREAD);
/kernel/trunk/arch/sparc64/include/context_offset.h
8,3 → 8,4
#define OFFSET_SP 0x28
#define OFFSET_PC 0x30
#define OFFSET_FP 0x38
#define OFFSET_I7 0x40
/kernel/trunk/arch/sparc64/include/asm.h
29,9 → 29,34
#ifndef __sparc64_ASM_H__
#define __sparc64_ASM_H__
 
#include <typedefs.h>
#include <arch/types.h>
#include <arch/register.h>
#include <config.h>
 
/** Read Processor State register.
*
* @return Value of PSTATE register.
*/
static inline __u64 pstate_read(void)
{
__u64 v;
__asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
return v;
}
 
/** Write Processor State register.
*
* @param New value of PSTATE register.
*/
static inline void pstate_write(__u64 v)
{
__asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
}
 
 
/** Enable interrupts.
*
* Enable interrupts and return previous
40,6 → 65,15
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_enable(void) {
pstate_reg_t pstate;
__u64 value;
value = pstate_read();
pstate.value = value;
pstate.ie = true;
pstate_write(pstate.value);
return (ipl_t) value;
}
 
/** Disable interrupts.
50,6 → 84,15
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_disable(void) {
pstate_reg_t pstate;
__u64 value;
value = pstate_read();
pstate.value = value;
pstate.ie = false;
pstate_write(pstate.value);
return (ipl_t) value;
}
 
/** Restore interrupt priority level.
59,6 → 102,11
* @param ipl Saved interrupt priority level.
*/
static inline void interrupts_restore(ipl_t ipl) {
pstate_reg_t pstate;
pstate.value = pstate_read();
pstate.ie = ((pstate_reg_t) ipl).ie;
pstate_write(pstate.value);
}
 
/** Return interrupt priority level.
68,6 → 116,7
* @return Current interrupt priority level.
*/
static inline ipl_t interrupts_read(void) {
return (ipl_t) pstate_read();
}
 
/** Return base address of current stack.
80,7 → 129,7
{
__address v;
__asm__ volatile ("and %%o6, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
__asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
return v;
}
/kernel/trunk/arch/sparc64/include/context.h
66,7 → 66,8
__u64 o5;
__address sp; /* %o6 */
__address pc; /* %o7 */
__address fp;
__address fp; /* %i6 */
__address i7;
ipl_t ipl;
};
 
/kernel/trunk/arch/sparc64/include/register.h
46,4 → 46,24
};
typedef union ver_reg ver_reg_t;
 
/** Processor State Register. */
union pstate_reg {
__u64 value;
struct {
__u64 : 52;
unsigned ig : 1; /**< Interrupt Globals. */
unsigned mg : 1; /**< MMU Globals. */
unsigned cle : 1; /**< Current Little Endian. */
unsigned tle : 1; /**< Trap Little Endian. */
unsigned mm : 2; /**< Memory Model. */
unsigned red : 1; /**< RED state. */
unsigned pef : 1; /**< Enable floating-point. */
unsigned am : 1; /**< 32-bit Address Mask. */
unsigned priv : 1; /**< Privileged Mode. */
unsigned ie : 1; /**< Interrupt Enable. */
unsigned ag : 1; /**< Alternate Globals*/
} __attribute__ ((packed));
};
typedef union pstate_reg pstate_reg_t;
 
#endif
/kernel/trunk/arch/sparc64/src/context.S
51,6 → 51,7
stx %o7, [\r + OFFSET_PC]
stx %sp, [\r + OFFSET_SP]
stx %fp, [\r + OFFSET_FP]
stx %i7, [\r + OFFSET_I7]
.endm
 
.macro CONTEXT_LOAD r
62,6 → 63,7
ldx [\r + OFFSET_PC], %o7
ldx [\r + OFFSET_SP], %sp
ldx [\r + OFFSET_FP], %fp
ldx [\r + OFFSET_I7], %i7
.endm
 
context_save_arch:
/kernel/trunk/arch/sparc64/src/dummy.s
58,8 → 58,6
fpu_init:
userspace:
 
 
dummy:
0:
retl
nop