HelenOS-historicHelenOSHelenOS-doc

Català-Valencià – Catalan中文 – Chinese (Simplified)中文 – Chinese (Traditional)Česky – CzechDansk – DanishNederlands – DutchEnglish – EnglishSuomi – FinnishFrançais – FrenchDeutsch – Germanעברית – Hebrewहिंदी – HindiMagyar – HungarianBahasa Indonesia – IndonesianItaliano – Italian日本語 – Japanese한국어 – KoreanМакедонски – Macedonianमराठी – MarathiNorsk – NorwegianPolski – PolishPortuguês – PortuguesePortuguês – Portuguese (Brazil)Русский – RussianSlovenčina – SlovakSlovenščina – SlovenianEspañol – SpanishSvenska – SwedishTürkçe – TurkishУкраїнська – UkrainianOëzbekcha – Uzbek

Compare Revisions

• This comparison shows the changes necessary to convert path

  → /kernel/ @ 928

  → /kernel/ @ 927

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 928 → Rev 927

/kernel/trunk/arch/ia64/src/mm/tlb.c
38,8 → 38,6
#include <arch/mm/page.h>
#include <arch/barrier.h>
#include <arch/interrupt.h>
#include <arch/pal/pal.h>
#include <arch/asm.h>
#include <typedefs.h>
#include <panic.h>
#include <arch.h>
47,38 → 45,7
/** Invalidate all TLB entries. */
void tlb_invalidate_all(void)
{
__address adr;
__u32 count1,count2,stride1,stride2;
int i,j;
adr=PAL_PTCE_INFO_BASE();
count1=PAL_PTCE_INFO_COUNT1();
count2=PAL_PTCE_INFO_COUNT2();
stride1=PAL_PTCE_INFO_STRIDE1();
stride2=PAL_PTCE_INFO_STRIDE2();
interrupts_disable();
for(i=0;i<count1;i++)
{
for(j=0;j<count2;j++)
{
asm volatile
(
"ptc.e %0;;"
:
:"r" (adr)
);
adr+=stride2;
}
adr+=stride1;
}
interrupts_enable();
srlz_d();
srlz_i();
/* TODO */
}
/** Invalidate entries belonging to an address space.

/kernel/trunk/arch/ia64/include/pal/pal.h
88,14 → 88,4
#define PAL_ENTER_IA_32_ENV 33
#define PAL_PMI_ENTRYPOINT 32
/*
Ski PTCE data
*/
#define PAL_PTCE_INFO_BASE() (0x100000000LL)
#define PAL_PTCE_INFO_COUNT1() (2)
#define PAL_PTCE_INFO_COUNT2() (3)
#define PAL_PTCE_INFO_STRIDE1() (0x10000000)
#define PAL_PTCE_INFO_STRIDE2() (0x2000)
#endif

/kernel/trunk/test/mm/purge1/test.c
File deleted

/kernel/trunk/kernel.config
89,6 → 89,5
@ "mm/slab1" SLAB test1 - No CPU-cache
@ "mm/slab2" SLAB test2 - SMP CPU cache
@ "fault/fault1" Write to NULL (maybe page fault)
@ "mm/purge1" Itanium TLB purge test
@ [ARCH=mips32] "debug/mips1" Mips breakpoint-debug test
! CONFIG_TEST (choice)