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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /boot/trunk/arch/ @ 1003

  → /boot/trunk/arch/ @ 1002

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 1003 → Rev 1002

/boot/trunk/arch/ppc32/loader/asm.S
27,6 → 27,7
#
#include "regname.h"
#include "spr.h"
.data
163,18 → 164,18
# Invalidate instruction cache
li r3, 0
ori r3, r3, (hid0_ice | hid0_dce | hid0_icfi | hid0_dci)
mfspr r4, hid0
ori r3, r3, (HID0_ICE | HID0_DCE | HID0_ICFI | HID0_DCI)
mfspr r4, SPRN_HID0
or r5, r4, r3
isync
mtspr hid0, r5
mtspr SPRN_HID0, r5
sync
isync
# Enable instruction cache
ori r5, r4, hid0_ice
mtspr hid0, r5
ori r5, r4, HID0_ICE
mtspr SPRN_HID0, r5
sync
isync
blr
183,3 → 184,4
mr r10, r4
mtlr r3
blr

/boot/trunk/arch/ppc32/loader/spr.h
0,0 → 1,47
/*
* Copyright (C) 2006 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SPR_H__
#define __SPR_H__
#define MSR_DR (1 << 4)
#define MSR_IR (1 << 5)
#define SPRN_SRR0 0x1a
#define SPRN_SRR1 0x1b
#define SPRN_HID0 0x3f0
#define HID0_ICE (1 << 15)
#define HID0_DCE (1 << 14)
#define HID0_ICFI (1 << 11)
#define HID0_DCI (1 << 10)
#define L1_CACHE_LINES (128 * 8)
#define L1_CACHE_BYTES 5
#endif

/boot/trunk/arch/ppc32/loader/regname.h
26,8 → 26,8
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_REGNAME_H__
#define __ppc32_REGNAME_H__
#ifndef __REGNAME_H__
#define __REGNAME_H__
/* Condition Register Bit Fields */
#define cr0 0
188,20 → 188,5
#define sprg2 274
#define sprg3 275
#define prv 287
#define hid0 1008
/* MSR bits */
#define msr_ir (1 << 4)
#define msr_dr (1 << 5)
/* HID0 bits */
#define hid0_ice (1 << 15)
#define hid0_dce (1 << 14)
#define hid0_icfi (1 << 11)
#define hid0_dci (1 << 10)
/* Cache sizes */
#define L1_CACHE_LINES (128 * 8)
#define L1_CACHE_BYTES 5
#endif