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Ignore whitespace Rev 914 → Rev 913

/boot/trunk/arch/ppc32/loader/asm.S
29,11 → 29,6
#include "regname.h"
#include "spr.h"
 
.data
 
flush_buffer:
.space 4
 
.text
 
.global memsetb
149,44 → 144,10
halt:
b halt
 
flush_instruction_cache:
 
# Flush data cache
lis r3, flush_buffer@h
ori r3, r3, flush_buffer@l
li r4, L1_CACHE_LINES
mtctr r4
0:
lwz r4, 0(r3)
addi r3, r3, L1_CACHE_BYTES
bdnz 0b
# Invalidate instruction cache
li r3, 0
ori r3, r3, (HID0_ICE | HID0_DCE | HID0_ICFI | HID0_DCI)
mfspr r4, SPRN_HID0
or r5, r4, r3
isync
mtspr SPRN_HID0, r5
sync
isync
# Enable instruction cache
ori r5, r4, HID0_ICE
mtspr SPRN_HID0, r5
sync
isync
blr
 
jump_to_kernel:
mfmsr r4
andis. r4, r4, (~MSR_DR | MSR_IR) >> 16
mtspr SPRN_SRR0, r3
mtspr SPRN_SRR1, r4
bl flush_instruction_cache
rfi
sync
RFI
/boot/trunk/arch/ppc32/loader/spr.h
29,19 → 29,13
#ifndef __SPR_H__
#define __SPR_H__
 
#define MSR_DR (1 << 27)
#define MSR_IR (1 << 26)
#define MSR_DR (1<<27)
#define MSR_IR (1<<26)
 
#define SPRN_SRR0 0x1a
#define SPRN_SRR1 0x1b
#define SPRN_HID0 0x3f0
 
#define HID0_ICE (1 << 15)
#define HID0_DCE (1 << 14)
#define HID0_ICFI (1 << 11)
#define HID0_DCI (1 << 10)
/* Works for PPC32 */
#define L1_CACHE_BYTES (1 << 5)
 
#define L1_CACHE_LINES (128 * 8)
#define L1_CACHE_BYTES 5
 
#endif