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Ignore whitespace Rev 136 → Rev 137

/design/trunk/src/ch_ipc.xml
82,6 → 82,8
</itemizedlist>
 
<figure float="1">
<title>Low level IPC</title>
 
<mediaobject id="ipc1">
<imageobject role="pdf">
<imagedata fileref="images/ipc1.pdf" format="PDF" />
95,8 → 97,6
<imagedata fileref="images/ipc1.svg" format="SVG" />
</imageobject>
</mediaobject>
 
<title>Low level IPC</title>
</figure>
 
<para>The communication between task A, that is connected to task B
230,6 → 230,7
control is transferred to it.</para>
 
<figure float="1">
<title>Single point of entry</title>
<mediaobject id="ipc2">
<imageobject role="pdf">
<imagedata fileref="images/ipc2.pdf" format="PDF" />
244,7 → 245,6
</imageobject>
</mediaobject>
 
<title>Single point of entry</title>
</figure>
 
<para>Very similar situation arises when a task decides to send a lot of
270,6 → 270,7
and the decision making is hidden from developers view.</para>
 
<figure float="1">
<title>Single point of entry solution</title>
<mediaobject id="ipc3">
<imageobject role="pdf">
<imagedata fileref="images/ipc3.pdf" format="PDF" />
284,7 → 285,6
</imageobject>
</mediaobject>
 
<title>Single point of entry solution</title>
</figure>
</section>
 
/design/trunk/src/ap_arch.xml
64,7 → 64,30
of the FS register which must be written using priviledged machine
specific instructions. Special syscall to change this register is
provided to user applications. The TLS address for this platform is
expected to point just after the end of the thread local data.</para>
expected to point just after the end of the thread local data. The
application sometimes need to get a real address of the thread local
data in its address space but it is impossible to read the base of the
FS segmentation register. The solution is to add the self-reference
address to the end of thread local data, so that the application can
read the address as %gs:0. </para>
 
<figure float="1">
<title>IA32 &amp; AMD64</title>
 
<mediaobject id="tldia32">
<imageobject role="pdf">
<imagedata fileref="images/tld_ia32.pdf" format="PDF" />
</imageobject>
 
<imageobject role="html">
<imagedata fileref="images/tld_ia32.png" format="PNG" />
</imageobject>
 
<imageobject role="fop">
<imagedata fileref="images/tld_ia32.svg" format="SVG" />
</imageobject>
</mediaobject>
</figure>
</section>
 
<section>
125,6 → 148,24
checking that the application is requesting a TLS pointer, it returns
the contents of the K1 register. The K1 register is expected to point
0x7000 bytes after the beginning of the thread local data.</para>
 
<figure float="1">
<title>MIPS &amp; PPC</title>
 
<mediaobject id="tldmips">
<imageobject role="pdf">
<imagedata fileref="images/tld_mips.pdf" format="PDF" />
</imageobject>
 
<imageobject role="html">
<imagedata fileref="images/tld_mips.png" format="PNG" />
</imageobject>
 
<imageobject role="fop">
<imagedata fileref="images/tld_mips.svg" format="SVG" />
</imageobject>
</mediaobject>
</figure>
</section>
</section>
 
132,6 → 173,14
<title>Power PC</title>
 
<para></para>
 
<section>
<title>Thread Local Storage</title>
 
<para>The Power PC thread local storage uses R2 register to hold an
address, that is 0x7000 bytes after the beginning of the thread local
data. Overally it is the same as on the MIPS architecture.</para>
</section>
</section>
 
<section>
138,5 → 187,23
<title>IA-64</title>
 
<para></para>
 
<figure float="1">
<title>IA64</title>
 
<mediaobject id="tldia64">
<imageobject role="pdf">
<imagedata fileref="images/tld_ia64.pdf" format="PDF" />
</imageobject>
 
<imageobject role="html">
<imagedata fileref="images/tld_ia64.png" format="PNG" />
</imageobject>
 
<imageobject role="fop">
<imagedata fileref="images/tld_ia64.svg" format="SVG" />
</imageobject>
</mediaobject>
</figure>
</section>
</appendix>