| 2,32 → 2,6 |
|---|
| |
| <chapter id="architecture"><?dbhtml filename="arch.html"?> |
| <title>Architecture overview</title> |
| <section> |
| <title>Task</title> |
| <para>Task ID - unique 64 bit number. Used for syscalls.</para> |
| <para>Contains threads</para> |
| <para>Address space is created per task</para> |
| <para>Memory mapping is per task</para> |
| <para>Context per thread. (Note 2 stacks on IA64).</para> |
| <para>IPC answer box associated per task</para> |
| </section> |
| <section> |
| <title>Memory management</title> |
| <para> |
| Zones - linked list (not many zones, so we can afford it. Can be replaced with B-tree in the future) |
| Number of zones depends on HW tables. Describe zone allocation/deallocation algoritm |
| </para> |
| <para>Page tables. 4 level hierarchical and hash directly supported. B+ Tree can be implemented. |
| <para>For paging there is an abstract layer</para> |
| <para>TLB shootdown implementation (update TLB upon mapping update/remove). |
| TLB shootdown ASID/ASID:PAGE/ALL. |
| TLB shootdown requests can come in asynchroniously |
| so there is a cache of TLB shootdown requests. Upon cache overflow TLB shootdown ALL is executed</para> |
| |
| <para> |
| Address spaces. Address space area (B+ tree). Only for uspace. Set of syscalls (shrink/extend etc). |
| Special address space area type - device - prohibits shrink/extend syscalls to call on it. |
| Address space has link to mapping tables (hierarchical - per Address space, hash - global tables). |
| </para> |
| <para>Couple of words about microkernel concept etc </para> |
| </chapter> |
| |
