Subversion Repositories HelenOS

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Ignore whitespace Rev 328 → Rev 329

/SPARTAN/trunk/test/fpu/mips1/test.c
86,18 → 86,18
 
for (i = 0; i<ATTEMPTS; i++) {
__asm__ volatile (
"ctc1 %0,$1"
"mtc1 %0,$1"
:"=r"(arg)
);
 
scheduler();
__asm__ volatile (
"cfc1 %0,$1"
"mfc1 %0,$1"
:"=r"(after_arg)
);
if(arg != after_arg)
panic("Control reg tid%d: arg(%d) != %d\n",
panic("General reg tid%d: arg(%d) != %d\n",
THREAD->tid, arg, after_arg);
}
 
/SPARTAN/trunk/arch/mips/_link.ld.in
15,7 → 15,7
ENTRY(kernel_image_start)
 
SECTIONS {
. = 0x80100000;
. = KERNEL_LOAD_ADDRESS;
.text : {
ktext_start = .;
*(.text);
29,12 → 29,14
hardcoded_kdata_size = .;
LONG(kdata_end - kdata_start);
hardcoded_load_address = .;
LONG(0x80100000);
LONG(KERNEL_LOAD_ADDRESS);
*(.rodata*);
*(.sdata);
*(.reginfo);
}
_gp = . + 0x8000;
.lit8 : { *(.lit8) }
.lit4 : { *(.lit4) }
.sdata : { *(.sdata) }
.sbss : {
*(.sbss);
*(.scommon);
43,15 → 45,17
*(.bss); /* uninitialized static variables */
*(COMMON); /* global variables */
}
mysymtable : {
 
mysymtab : {
symbol_table = .;
*(symtab.*); /* Symbol table, must be LAST symbol!*/
*(symtab.*); /* Symbol table, must be LAST symbol!*/
}
kdata_end = .;
 
.mdebug : { *(.mdebug) }
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.comment : { *(.comment) }
.note : { *(.note) }
/DISCARD/ : {
*(.mdebug*);
*(.pdr);
*(.comment);
*(.note);
}
}
/SPARTAN/trunk/arch/mips/boot/boot.S
33,6 → 33,10
.set nomacro
 
#include <arch/asm/boot.h>
 
#ifndef KERNEL_LOAD_ADDRESS
# define KERNEL_LOAD_ADDRESS 0x80010000
#endif
.global start
start:
/SPARTAN/trunk/arch/mips/boot/Makefile
13,7 → 13,7
LD=$(MIPS_BINUTILS_DIR)/$(MIPS_TARGET)-ld
 
ASFLAGS=-mips2 -I../../../include
LFLAGS=--oformat=binary -mips2 -e start -T _link.ld
LFLAGS=--oformat=binary -e start -T _link.ld
 
.S.o:
$(CC) $(ASFLAGS) -c -o $@ $<
/SPARTAN/trunk/arch/mips/include/asm/boot.h
33,8 → 33,4
/* Temporary stack size for boot process */
#define TEMP_STACK_SIZE 0x100
 
/* Kernel startup address */
#define KERNEL_LOAD_ADDRESS 0x80100000
 
 
#endif
/SPARTAN/trunk/arch/mips/include/interrupt.h
29,6 → 29,8
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
 
#define TIMER_INTERRUPT 7
 
extern void interrupt(void);
 
#endif
/SPARTAN/trunk/arch/mips/include/console.h
38,4 → 38,7
 
void console_init(void);
 
extern int bios_write(int fd, const char *buf, int size, int *cnt);
 
 
#endif
/SPARTAN/trunk/arch/mips/include/cp0.h
38,7 → 38,9
#define cp0_status_bev_bootstrap_bit (1<<22)
#define cp0_status_fpu_bit (1<<29)
 
#define cp0_status_im7_shift 15
#define cp0_status_im_shift 8
#define cp0_status_im_mask 0xff00
 
/*
* Magic value for use in msim.
* On AMD Duron 800Mhz, this roughly seems like one us.
63,6 → 65,10
__asm__ volatile ("tlbwr");
}
 
#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
 
 
extern __u32 cp0_index_read(void);
/SPARTAN/trunk/arch/mips/include/mm/memory_init.h
32,5 → 32,6
#include <config.h>
 
#define get_memory_size() CONFIG_MEMORY_SIZE
//#define get_memory_size() 150*1024*1024
 
#endif
/SPARTAN/trunk/arch/mips/Makefile.inc
11,39 → 11,46
BFD_NAME=elf32-tradlittlemips
BFD_ARCH=mips
 
ASFLAGS=-mips3
DEFS=-DARCH=$(ARCH) -DMACHINE=${MACHINE} -DKERNEL_LOAD_ADDRESS=${KERNEL_LOAD_ADDRESS}
CFLAGS=$(DEFS) -mno-abicalls -G 0 -nostdlib -fno-builtin -O2 -fno-zero-initialized-in-bss
LFLAGS=-M -N
 
DEFS=-DARCH=$(ARCH) -DMACHINE=${MACHINE}
CFLAGS=$(DEFS) -mno-abicalls -mips3 -G 0 -nostdlib -fno-builtin -O2
LFLAGS=-mips2 -M -no-check-sections
 
# It seems that on big endian either GCC or the simulators
# have the swl/swr/lwl/lwr instructions wrong. Just for sure,
# disable it with -mmemcpy (force calling memcpy instead of inlining)
 
ifeq (${MACHINE},indy)
CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY
BFD = elf32-big
CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY -march=r4600
BFD = ecoff-bigmips
KERNEL_LOAD_ADDRESS = 0x88002000
endif
 
ifeq (${MACHINE},lgxemul)
CFLAGS += -DHAVE_FPU -DFPU_LAZY
CFLAGS += -DHAVE_FPU -DFPU_LAZY -mips3
BFD = ecoff-littlemips
KERNEL_LOAD_ADDRESS = 0x80010000
endif
 
ifeq (${MACHINE},bgxemul)
CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY
CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY -mips3
BFD = ecoff-bigmips
KERNEL_LOAD_ADDRESS = 0x80010000
endif
 
# MSIM needs lwl/swl patch & 4kc instruction patch to work
# otherwise add -mmemcpy -mips3
ifeq (${MACHINE},msim)
BFD = binary
CFLAGS += -msoft-float
CFLAGS += -msoft-float -march=4kc
KERNEL_LOAD_ADDRESS = 0x80010000
endif
 
# SIMICS 4kc emulation is broken, although for instructions
# that do not bother us
ifeq (${MACHINE},simics)
BFD = elf32-little
CFLAGS += -msoft-float
CFLAGS += -msoft-float -mips3
KERNEL_LOAD_ADDRESS = 0x80010000
endif
 
../arch/$(ARCH)/_link.ld: ../arch/$(ARCH)/_link.ld.in
/SPARTAN/trunk/arch/mips/src/asm.S
117,6 → 117,13
cp0_prid_read: cp0_read $15
 
 
.global bios_write
bios_write:
lw $2, 0x80001020
lw $2, 0x6c($2)
j $2
nop
.global cpu_halt
cpu_halt:
j cpu_halt
/SPARTAN/trunk/arch/mips/src/console.c
30,7 → 30,20
#include <arch/types.h>
#include <arch/cp0.h>
#include <arch/console.h>
#include <arch.h>
 
static void arc_putchar(const char ch)
{
int cnt;
pri_t pri;
 
/* TODO: Should be spinlock? */
pri = cpu_priority_high();
bios_write(1, &ch, 1, &cnt);
cpu_priority_restore(pri);
}
 
static void cons_putchar(const char ch)
{
*((char *) VIDEORAM) = ch;
/SPARTAN/trunk/arch/mips/src/cpu/cpu.c
77,7 → 77,8
{ "QED", "R4600" }, /* 0x20 */
{ "Sony", "R3000" }, /* 0x21 */
{ "Toshiba", "R3000" }, /* 0x22 */
{ "NKK", "R3000" } /* 0x23 */
{ "NKK", "R3000" }, /* 0x23 */
{ NULL, NULL }
};
 
static struct data_t imp_data80[] = {
84,7 → 85,8
{ "MIPS", "4Kc" }, /* 0x80 */
{"Invalid","Invalid"}, /* 0x81 */
{"Invalid","Invalid"}, /* 0x82 */
{"MIPS","4Km & 4Kp"} /* 0x83 */
{"MIPS","4Km & 4Kp"}, /* 0x83 */
{ NULL, NULL}
};
 
void cpu_arch_init(void)
100,11 → 102,26
void cpu_print_report(cpu_t *m)
{
struct data_t *data;
int i;
 
if (m->arch.imp_num & 0x80) {
/* Count records */
for (i=0;imp_data80[i].vendor;i++)
;
if (m->arch.imp_num & 0x7f >= i) {
printf("imp=%d\n",m->arch.imp_num);
return;
}
data = &imp_data80[m->arch.imp_num & 0x7f];
} else
} else {
for (i=0;imp_data[i].vendor;i++)
;
if (m->arch.imp_num >= i) {
printf("imp=%d\n",m->arch.imp_num);
return;
}
data = &imp_data[m->arch.imp_num];
}
 
printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n",
m->id, data->vendor, data->model, m->arch.rev_num >> 4,
/SPARTAN/trunk/arch/mips/src/mips.c
35,6 → 35,7
#include <userspace.h>
#include <arch/console.h>
#include <memstr.h>
#include <arch/interrupt.h>
 
/* Size of the code jumping to the exception handler code
* - J+NOP
47,14 → 48,17
 
#include <arch/debug.h>
 
#include <print.h>
void arch_pre_mm_init(void)
{
/* It is not assumed by default */
cpu_priority_high();
 
/* Copy the exception vectors to the right places */
memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE);
memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE);
memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
 
 
/*
* Switch to BEV normal level so that exception vectors point to the kernel.
* Clear the error level.
61,10 → 65,14
*/
cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit));
 
/*
* Mask all interrupts
*/
cp0_mask_all_int();
/*
* Unmask hardware clock interrupt.
*/
cp0_status_write(cp0_status_read() | (1<<cp0_status_im7_shift));
cp0_unmask_int(TIMER_INTERRUPT);
 
/*
* Start hardware clock.
/SPARTAN/trunk/arch/mips/src/mm/frame.c
28,9 → 28,11
 
#include <arch/mm/frame.h>
#include <mm/frame.h>
#include <arch/asm/boot.h>
#include <arch/mm/page.h>
 
void frame_arch_init(void)
{
/* Disable first megabyte (God knows why) */
frame_region_not_free(0, 1024*1024);
/* Disable Everything until load address */
frame_region_not_free(0, KA2PA(KERNEL_LOAD_ADDRESS));
}
/SPARTAN/trunk/arch/mips/src/interrupt.c
81,9 → 81,9
case 6: /* IRQ4 */
panic("unhandled interrupt %d\n", i);
break;
case 7: /* Timer Interrupt */
cp0_compare_write(cp0_count_read() + cp0_compare_value); /* clear timer interrupt */
/* start counting over again */
case TIMER_INTERRUPT:
/* clear timer interrupt & set new */
cp0_compare_write(cp0_count_read() + cp0_compare_value);
clock();
break;
}