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Ignore whitespace Rev 3576 → Rev 3577

/trunk/kernel/kernel.config
118,7 → 118,7
! [(ARCH=ia32|ARCH=amd64)&CONFIG_FB=y] CONFIG_VESA_BPP (choice)
 
# Support for SMP
! [ARCH=ia32|ARCH=amd64|ARCH=ia32xen|ARCH=sparc64] CONFIG_SMP (y/n)
! [ARCH=ia32|ARCH=amd64|ARCH=ia32xen|ARCH=sparc64|ARCH=ia64] CONFIG_SMP (y/n)
 
# Improved support for hyperthreading
! [(ARCH=ia32|ARCH=amd64|ARCH=ia32xen)&CONFIG_SMP=y] CONFIG_HT (y/n)
139,8 → 139,9
! [ARCH=sparc64] CONFIG_Z8530 (y/n)
 
# Support for NS16550 serial port
! [ARCH=sparc64] CONFIG_NS16550 (y/n)
! [ARCH=sparc64|ARCH=ia64] CONFIG_NS16550 (y/n)
 
 
# Virtually indexed D-cache support
! [ARCH=sparc64] CONFIG_VIRT_IDX_DCACHE (y/n)
 
/trunk/kernel/genarch/include/kbd/ns16550.h
48,7 → 48,75
extern irq_ownership_t ns16550_claim(void);
extern void ns16550_irq_handler(irq_t *irq, void *arg, ...);
 
#include <arch/types.h>
#ifndef ia64
#include <arch/drivers/kbd.h>
#endif
/* NS16550 registers */
#define RBR_REG 0 /** Receiver Buffer Register. */
#define IER_REG 1 /** Interrupt Enable Register. */
#define IIR_REG 2 /** Interrupt Ident Register (read). */
#define FCR_REG 2 /** FIFO control register (write). */
#define LCR_REG 3 /** Line Control register. */
#define LSR_REG 5 /** Line Status Register. */
 
#define IER_ERBFI 0x01 /** Enable Receive Buffer Full Interrupt. */
 
#define LCR_DLAB 0x80 /** Divisor Latch Access bit. */
 
/** Structure representing the ns16550 device. */
typedef struct {
devno_t devno;
volatile ioport_t io_port; /** Memory mapped registers of the ns16550. */
} ns16550_t;
 
static inline uint8_t ns16550_rbr_read(ns16550_t *dev)
{
return inb(dev->io_port+RBR_REG);
}
static inline void ns16550_rbr_write(ns16550_t *dev, uint8_t v)
{
outb(dev->io_port+RBR_REG,v);
}
 
static inline uint8_t ns16550_ier_read(ns16550_t *dev)
{
return inb(dev->io_port+IER_REG);
}
 
static inline void ns16550_ier_write(ns16550_t *dev, uint8_t v)
{
outb(dev->io_port+IER_REG,v);
}
 
static inline uint8_t ns16550_iir_read(ns16550_t *dev)
{
return inb(dev->io_port+IIR_REG);
}
 
static inline void ns16550_fcr_write(ns16550_t *dev, uint8_t v)
{
outb(dev->io_port+FCR_REG,v);
}
 
static inline uint8_t ns16550_lcr_read(ns16550_t *dev)
{
return inb(dev->io_port+LCR_REG);
}
 
static inline void ns16550_lcr_write(ns16550_t *dev, uint8_t v)
{
outb(dev->io_port+LCR_REG,v);
}
 
static inline uint8_t ns16550_lsr_read(ns16550_t *dev)
{
return inb(dev->io_port+LSR_REG);
}
 
 
 
#endif
 
/** @}
*/
/trunk/kernel/genarch/src/kbd/ns16550.c
38,8 → 38,10
#include <genarch/kbd/key.h>
#include <genarch/kbd/scanc.h>
#include <genarch/kbd/scanc_sun.h>
#ifndef ia64
#include <arch/drivers/kbd.h>
#include <arch/drivers/ns16550.h>
#endif
#include <ddi/irq.h>
#include <ipc/irq.h>
#include <cpu.h>
109,13 → 111,13
* @param inr Interrupt number.
* @param vaddr Virtual address of device's registers.
*/
void ns16550_init(devno_t devno, inr_t inr, uintptr_t vaddr)
void ns16550_init(devno_t devno, inr_t inr, ioport_t port)
{
chardev_initialize("ns16550_kbd", &kbrd, &ops);
stdin = &kbrd;
ns16550.devno = devno;
ns16550.reg = (uint8_t *) vaddr;
ns16550.io_port = port;
irq_initialize(&ns16550_irq);
ns16550_irq.devno = devno;
125,10 → 127,21
irq_register(&ns16550_irq);
sysinfo_set_item_val("kbd", NULL, true);
#ifndef ia64
sysinfo_set_item_val("kbd.type", NULL, KBD_NS16550);
#endif
sysinfo_set_item_val("kbd.devno", NULL, devno);
sysinfo_set_item_val("kbd.inr", NULL, inr);
sysinfo_set_item_val("kbd.address.virtual", NULL, vaddr);
sysinfo_set_item_val("kbd.address.virtual", NULL, port);
 
#ifdef ia64
uint8_t c;
c=ns16550_lcr_read(&ns16550);
ns16550_lcr_write(&ns16550,0x80|c);
ns16550_rbr_write(&ns16550,0x0c);
ns16550_ier_write(&ns16550,0x00);
ns16550_lcr_write(&ns16550,c);
#endif
ns16550_grab();
}
152,6 → 165,7
{
}
 
 
char ns16550_key_read(chardev_t *d)
{
char ch;
161,6 → 175,7
while (!(ns16550_lsr_read(&ns16550) & LSR_DATA_READY))
;
x = ns16550_rbr_read(&ns16550);
#ifndef ia64
if (x != IGNORE_CODE) {
if (x & KEY_RELEASE)
key_released(x ^ KEY_RELEASE);
167,6 → 182,15
else
active_read_key_pressed(x);
}
#else
extern chardev_t kbrd;
if(x!=0x0d)
{
if(x==0x7f) x='\b';
chardev_push_character(&kbrd,x);
}
#endif
 
}
return ch;
}
201,6 → 225,7
uint8_t x;
x = ns16550_rbr_read(&ns16550);
#ifndef ia64
if (x != IGNORE_CODE) {
if (x & KEY_RELEASE)
key_released(x ^ KEY_RELEASE);
207,6 → 232,15
else
key_pressed(x);
}
#else
extern chardev_t kbrd;
if(x!=0x0d)
{
if(x==0x7f) x='\b';
chardev_push_character(&kbrd,x);
}
#endif
 
}
}
 
/trunk/kernel/genarch/src/kbd/key.c
39,9 → 39,13
#ifdef CONFIG_I8042
#include <genarch/kbd/scanc_pc.h>
#endif
 
#if (defined(sparc64))
#if (defined(CONFIG_Z8530) || defined(CONFIG_NS16550))
#include <genarch/kbd/scanc_sun.h>
#endif
#endif
 
#include <synch/spinlock.h>
#include <console/chardev.h>
#include <macros.h>
/trunk/kernel/arch/sparc64/include/asm.h
43,6 → 43,45
#include <config.h>
#include <arch/stack.h>
 
typedef uint64_t ioport_t;
 
 
static inline void outb(ioport_t port,uint8_t v)
{
*((uint8_t *)(port)) = v;
}
 
static inline void outw(ioport_t port,uint16_t v)
{
*((uint16_t *)(port)) = v;
}
 
static inline void outl(ioport_t port,uint32_t v)
{
*((uint32_t *)(port)) = v;
}
 
 
 
static inline uint8_t inb(ioport_t port)
{
return *((uint8_t *)(port));
}
 
static inline uint16_t inw(ioport_t port)
{
return *((uint16_t *)(port));
}
 
static inline uint32_t inl(ioport_t port)
{
return *((uint32_t *)(port));
}
 
 
 
 
 
/** Read Processor State register.
*
* @return Value of PSTATE register.
/trunk/kernel/arch/sparc64/include/drivers/ns16550.h
35,67 → 35,7
#ifndef KERN_sparc64_NS16550_H_
#define KERN_sparc64_NS16550_H_
 
#include <arch/types.h>
#include <arch/drivers/kbd.h>
 
/* NS16550 registers */
#define RBR_REG 0 /** Receiver Buffer Register. */
#define IER_REG 1 /** Interrupt Enable Register. */
#define IIR_REG 2 /** Interrupt Ident Register (read). */
#define FCR_REG 2 /** FIFO control register (write). */
#define LCR_REG 3 /** Line Control register. */
#define LSR_REG 5 /** Line Status Register. */
 
#define IER_ERBFI 0x01 /** Enable Receive Buffer Full Interrupt. */
 
#define LCR_DLAB 0x80 /** Divisor Latch Access bit. */
 
/** Structure representing the ns16550 device. */
typedef struct {
devno_t devno;
volatile uint8_t *reg; /** Memory mapped registers of the ns16550. */
} ns16550_t;
 
static inline uint8_t ns16550_rbr_read(ns16550_t *dev)
{
return dev->reg[RBR_REG];
}
 
static inline uint8_t ns16550_ier_read(ns16550_t *dev)
{
return dev->reg[IER_REG];
}
 
static inline void ns16550_ier_write(ns16550_t *dev, uint8_t v)
{
dev->reg[IER_REG] = v;
}
 
static inline uint8_t ns16550_iir_read(ns16550_t *dev)
{
return dev->reg[IIR_REG];
}
 
static inline void ns16550_fcr_write(ns16550_t *dev, uint8_t v)
{
dev->reg[FCR_REG] = v;
}
 
static inline uint8_t ns16550_lcr_read(ns16550_t *dev)
{
return dev->reg[LCR_REG];
}
 
static inline void ns16550_lcr_write(ns16550_t *dev, uint8_t v)
{
dev->reg[LCR_REG] = v;
}
 
static inline uint8_t ns16550_lsr_read(ns16550_t *dev)
{
return dev->reg[LSR_REG];
}
 
#endif
 
/** @}
/trunk/kernel/arch/sparc64/src/drivers/kbd.c
147,7 → 147,7
#endif
#ifdef CONFIG_NS16550
case KBD_NS16550:
ns16550_init(devno, inr, vaddr);
ns16550_init(devno, inr, (ioport_t)vaddr);
break;
#endif
default:
/trunk/kernel/arch/ia64/include/asm.h
39,10 → 39,11
#include <arch/types.h>
#include <arch/register.h>
 
typedef uint64_t ioport_t;
 
#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
 
static inline void outb(uint64_t port,uint8_t v)
static inline void outb(ioport_t port,uint8_t v)
{
*((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
 
49,7 → 50,7
asm volatile ("mf\n" ::: "memory");
}
 
static inline void outw(uint64_t port,uint16_t v)
static inline void outw(ioport_t port,uint16_t v)
{
*((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
 
56,7 → 57,7
asm volatile ("mf\n" ::: "memory");
}
 
static inline void outl(uint64_t port,uint32_t v)
static inline void outl(ioport_t port,uint32_t v)
{
*((uint32_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
 
65,7 → 66,7
 
 
 
static inline uint8_t inb(uint64_t port)
static inline uint8_t inb(ioport_t port)
{
asm volatile ("mf\n" ::: "memory");
 
72,7 → 73,7
return *((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 ))));
}
 
static inline uint16_t inw(uint64_t port)
static inline uint16_t inw(ioport_t port)
{
asm volatile ("mf\n" ::: "memory");
 
79,7 → 80,7
return *((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xffE) | ( (port >> 2) << 12 ))));
}
 
static inline uint32_t inl(uint64_t port)
static inline uint32_t inl(ioport_t port)
{
asm volatile ("mf\n" ::: "memory");
 
98,9 → 99,14
{
uint64_t v;
 
asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
//I'm not sure why but this code bad inlines in scheduler,
//so THE shifts about 16B and causes kernel panic
//asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
//return v;
return v;
//this code have the same meaning but inlines well
asm volatile ("mov %0 = r12" : "=r" (v) );
return v & (~(STACK_SIZE-1));
}
 
/** Return Processor State Register.
152,6 → 158,16
return v;
}
 
static inline uint64_t cr64_read(void)
{
uint64_t v;
asm volatile ("mov %0 = cr64\n" : "=r" (v));
return v;
}
 
 
/** Write ITC (Interval Timer Counter) register.
*
* @param v New counter value.