| /trunk/kernel/generic/src/mm/backend_elf.c |
|---|
| 153,7 → 153,8 |
| memcpy((void *) PA2KA(frame), |
| (void *) (base + i * FRAME_SIZE), FRAME_SIZE); |
| if (entry->p_flags & PF_X) { |
| smc_coherence_block(PA2KA(frame), FRAME_SIZE); |
| smc_coherence_block((void *) PA2KA(frame), |
| FRAME_SIZE); |
| } |
| dirty = true; |
| } else { |
| 193,8 → 194,8 |
| (void *) (base + i * FRAME_SIZE + pad_lo), |
| FRAME_SIZE - pad_lo - pad_hi); |
| if (entry->p_flags & PF_X) { |
| smc_coherence_block(PA2KA(frame) + pad_lo, FRAME_SIZE - |
| pad_lo - pad_hi); |
| smc_coherence_block((void *) (PA2KA(frame) + pad_lo), |
| FRAME_SIZE - pad_lo - pad_hi); |
| } |
| memsetb((void *) PA2KA(frame), pad_lo, 0); |
| memsetb((void *) (PA2KA(frame) + FRAME_SIZE - pad_hi), pad_hi, |
| /trunk/kernel/arch/ppc32/include/barrier.h |
|---|
| 42,9 → 42,43 |
| #define read_barrier() asm volatile ("sync" ::: "memory") |
| #define write_barrier() asm volatile ("eieio" ::: "memory") |
| #define smc_coherence(a) |
| #define smc_coherence_block(a, l) |
| /* |
| * The IMB sequence used here is valid for all possible cache models |
| * on uniprocessor. SMP might require a different sequence. |
| * See PowerPC Programming Environment for 32-Bit Microprocessors, |
| * chapter 5.1.5.2 |
| */ |
| static inline void smc_coherence(void *addr) |
| { |
| asm volatile ( |
| "dcbst 0, %0\n" |
| "sync\n" |
| "icbi 0, %0\n" |
| "isync\n" |
| :: "r" (addr) |
| ); |
| } |
| #define COHERENCE_INVAL_MIN 4 |
| static inline void smc_coherence_block(void *addr, unsigned long len) |
| { |
| unsigned long i; |
| for (i = 0; i < len; i += COHERENCE_INVAL_MIN) { |
| asm volatile ("dcbst 0, %0\n" :: "r" (addr + i)); |
| } |
| asm volatile ("sync"); |
| for (i = 0; i < len; i += COHERENCE_INVAL_MIN) { |
| asm volatile ("icbi 0, %0\n" :: "r" (addr + i)); |
| } |
| asm volatile ("isync"); |
| } |
| #endif |
| /** @} |