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Ignore whitespace Rev 1881 → Rev 1882

/trunk/kernel/test/fpu/fpu1/test.c
45,15 → 45,15
#define PI_10e8 314159265
 
 
#ifdef __ia32_ARCH_H__
#ifdef KERN_ia32_ARCH_H_
static inline double sqrt(double x) { double v; __asm__ ("fsqrt\n" : "=t" (v) : "0" (x)); return v; }
#endif
 
#ifdef __amd64_ARCH_H__
#ifdef KERN_amd64_ARCH_H_
static inline double sqrt(double x) { double v; __asm__ ("fsqrt\n" : "=t" (v) : "0" (x)); return v; }
#endif
 
#ifdef __ia64_ARCH_H__
#ifdef KERN_ia64_ARCH_H_
static inline long double sqrt(long double a)
{
long double x = 1;
105,7 → 105,7
static void pi(void *data)
{
 
#ifdef __ia64_ARCH_H__
#ifdef KERN_ia64_ARCH_H_
#undef PI_10e8
#define PI_10e8 3141592
#endif
134,7 → 134,7
pi = 2 * n * ad;
}
 
#ifdef __ia64_ARCH_H__
#ifdef KERN_ia64_ARCH_H_
if((int)(1000000*pi)!=PI_10e8)
panic("tid%d: pi*10e8=%zd should be %zd\n", THREAD->tid, (unative_t) (1000000*pi),(unative_t) (PI_10e8/100));
#else
/trunk/kernel/kernel.config
85,7 → 85,7
! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_SIMICS_FIX (y/n)
 
# Lazy FPU context switching
! [(ARCH=mips32&MACHINE!=msim&MACHINE!=simics)|ARCH=amd64|ARCH=ia32|ARCH=ia64|ARCH=xen32] CONFIG_FPU_LAZY (y/n)
! [(ARCH=mips32&MACHINE!=msim&MACHINE!=simics)|ARCH=amd64|ARCH=ia32|ARCH=ia64|ARCH=sparc64|ARCH=xen32] CONFIG_FPU_LAZY (y/n)
 
# Power off on halt
! [ARCH=ppc32] CONFIG_POWEROFF (n/y)
/trunk/kernel/generic/include/fpu_context.h
35,7 → 35,6
#ifndef __FPU_CONTEXT_H__
#define __FPU_CONTEXT_H__
 
 
#include <arch/fpu_context.h>
#include <typedefs.h>
 
/trunk/kernel/generic/src/proc/scheduler.c
86,7 → 86,7
{
before_thread_runs_arch();
#ifdef CONFIG_FPU_LAZY
if(THREAD==CPU->fpu_owner)
if(THREAD == CPU->fpu_owner)
fpu_enable();
else
fpu_disable();
96,7 → 96,7
fpu_context_restore(THREAD->saved_fpu_context);
else {
fpu_init();
THREAD->fpu_context_exists=1;
THREAD->fpu_context_exists = 1;
}
#endif
}
127,7 → 127,7
spinlock_lock(&CPU->fpu_owner->lock);
fpu_context_save(CPU->fpu_owner->saved_fpu_context);
/* don't prevent migration */
CPU->fpu_owner->fpu_context_engaged=0;
CPU->fpu_owner->fpu_context_engaged = 0;
spinlock_unlock(&CPU->fpu_owner->lock);
CPU->fpu_owner = NULL;
}
146,9 → 146,9
goto restart;
}
fpu_init();
THREAD->fpu_context_exists=1;
THREAD->fpu_context_exists = 1;
}
CPU->fpu_owner=THREAD;
CPU->fpu_owner = THREAD;
THREAD->fpu_context_engaged = 1;
spinlock_unlock(&THREAD->lock);
 
/trunk/kernel/arch/sparc64/include/regdef.h
43,10 → 43,12
#define PSTATE_MG_BIT (1<<10)
 
#define PSTATE_PRIV_BIT (1<<2)
#define PSTATE_PEF_BIT (1<<4)
 
#define TSTATE_PSTATE_SHIFT 8
#define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT<<TSTATE_PSTATE_SHIFT)
#define TSTATE_IE_BIT (PSTATE_IE_BIT<<TSTATE_PSTATE_SHIFT)
#define TSTATE_PEF_BIT (PSTATE_PEF_BIT<<TSTATE_PSTATE_SHIFT)
 
#define TSTATE_CWP_MASK 0x1f
 
/trunk/kernel/arch/sparc64/include/fpu_context.h
37,7 → 37,12
 
#include <arch/types.h>
 
#define ARCH_HAS_FPU
#define FPU_CONTEXT_ALIGN 8
 
struct fpu_context {
uint64_t d[32];
uint64_t fsr;
};
 
#endif
/trunk/kernel/arch/sparc64/include/asm.h
108,6 → 108,28
__asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
}
 
/** Read FPRS Register.
*
* @return Value of FPRS register.
*/
static inline uint64_t fprs_read(void)
{
uint64_t v;
__asm__ volatile ("rd %%fprs, %0\n" : "=r" (v));
return v;
}
 
/** Write FPRS Register.
*
* @param v New value of FPRS register.
*/
static inline void fprs_write(uint64_t v)
{
__asm__ volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
}
 
/** Read SOFTINT Register.
*
* @return Value of SOFTINT register.
/trunk/kernel/arch/sparc64/include/trap/exception.h
40,6 → 40,7
#define TT_INSTRUCTION_ACCESS_ERROR 0x0a
#define TT_ILLEGAL_INSTRUCTION 0x10
#define TT_PRIVILEGED_OPCODE 0x11
#define TT_FP_DISABLED 0x20
#define TT_DIVISION_BY_ZERO 0x28
#define TT_DATA_ACCESS_EXCEPTION 0x30
#define TT_DATA_ACCESS_ERROR 0x32
56,6 → 57,7
extern void instruction_access_error(int n, istate_t *istate);
extern void illegal_instruction(int n, istate_t *istate);
extern void privileged_opcode(int n, istate_t *istate);
extern void fp_disabled(int n, istate_t *istate);
extern void division_by_zero(int n, istate_t *istate);
extern void data_access_exception(int n, istate_t *istate);
extern void data_access_error(int n, istate_t *istate);
/trunk/kernel/arch/sparc64/include/register.h
87,7 → 87,7
union tick_compare_reg {
uint64_t value;
struct {
unsigned int_dis : 1; /**< TICK_INT interrupt disabled flag. */
unsigned int_dis : 1; /**< TICK_INT interrupt disabled flag. */
uint64_t tick_cmpr : 63; /**< Compare value for TICK interrupts. */
} __attribute__ ((packed));
};
105,6 → 105,18
};
typedef union softint_reg softint_reg_t;
 
/** Floating-point Registers State Register. */
union fprs_reg {
uint64_t value;
struct {
uint64_t : 61;
unsigned fef : 1;
unsigned du : 1;
unsigned dl : 1;
} __attribute__ ((packed));
};
typedef union fprs_reg fprs_reg_t;
 
#endif
 
/** @}
/trunk/kernel/arch/sparc64/Makefile.inc
87,6 → 87,7
arch/$(ARCH)/src/panic.S \
arch/$(ARCH)/src/console.c \
arch/$(ARCH)/src/context.S \
arch/$(ARCH)/src/fpu_context.c \
arch/$(ARCH)/src/dummy.s \
arch/$(ARCH)/src/mm/as.c \
arch/$(ARCH)/src/mm/frame.c \
/trunk/kernel/arch/sparc64/src/fpu_context.c
0,0 → 1,200
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64
* @{
*/
/** @file
*
*/
 
#include <fpu_context.h>
#include <arch/register.h>
#include <arch/asm.h>
 
void fpu_context_save(fpu_context_t *fctx)
{
fprs_reg_t fprs;
fprs.value = fprs_read();
 
if (fprs.dl) {
/*
* The lower half of floating-point registers is dirty.
* Spill it to memory.
*/
__asm__ volatile (
"std %%f0, %0\n"
"std %%f2, %1\n"
"std %%f4, %2\n"
"std %%f6, %3\n"
"std %%f8, %4\n"
"std %%f10, %5\n"
"std %%f12, %6\n"
"std %%f14, %7\n"
"std %%f16, %8\n"
"std %%f18, %9\n"
"std %%f20, %10\n"
"std %%f22, %11\n"
"std %%f24, %12\n"
"std %%f26, %13\n"
"std %%f28, %14\n"
"std %%f30, %15\n"
: "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]),
"=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]),
"=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]),
"=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15])
);
fprs.dl = false;
}
if (fprs.du) {
/*
* The upper half of floating-point registers is dirty.
* Spill it to memory.
*/
__asm__ volatile (
"std %%f32, %0\n"
"std %%f34, %1\n"
"std %%f36, %2\n"
"std %%f38, %3\n"
"std %%f40, %4\n"
"std %%f42, %5\n"
"std %%f44, %6\n"
"std %%f46, %7\n"
"std %%f48, %8\n"
"std %%f50, %9\n"
"std %%f52, %10\n"
"std %%f54, %11\n"
"std %%f56, %12\n"
"std %%f58, %13\n"
"std %%f60, %14\n"
"std %%f62, %15\n"
: "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]),
"=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]),
"=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]),
"=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31])
);
fprs.du = false;
}
fprs_write(fprs.value);
__asm__ volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr));
}
 
void fpu_context_restore(fpu_context_t *fctx)
{
fprs_reg_t fprs;
fprs.value = fprs_read();
__asm__ volatile (
"ldd %0, %%f0\n"
"ldd %1, %%f2\n"
"ldd %2, %%f4\n"
"ldd %3, %%f6\n"
"ldd %4, %%f8\n"
"ldd %5, %%f10\n"
"ldd %6, %%f12\n"
"ldd %7, %%f14\n"
"ldd %8, %%f16\n"
"ldd %9, %%f18\n"
"ldd %10, %%f20\n"
"ldd %11, %%f22\n"
"ldd %12, %%f24\n"
"ldd %13, %%f26\n"
"ldd %14, %%f28\n"
"ldd %15, %%f30\n"
:
: "m" (fctx->d[0]), "m" (fctx->d[1]), "m" (fctx->d[2]), "m" (fctx->d[3]),
"m" (fctx->d[4]), "m" (fctx->d[5]), "m" (fctx->d[6]), "m" (fctx->d[7]),
"m" (fctx->d[8]), "m" (fctx->d[9]), "m" (fctx->d[10]), "m" (fctx->d[11]),
"m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15])
);
/*
* We need to split loading of the floating-point registers because
* GCC (4.1.1) can't handle more than 30 operands in one asm statement.
*/
__asm__ volatile (
"ldd %0, %%f32\n"
"ldd %1, %%f34\n"
"ldd %2, %%f36\n"
"ldd %3, %%f38\n"
"ldd %4, %%f40\n"
"ldd %5, %%f42\n"
"ldd %6, %%f44\n"
"ldd %7, %%f46\n"
"ldd %8, %%f48\n"
"ldd %9, %%f50\n"
"ldd %10, %%f52\n"
"ldd %11, %%f54\n"
"ldd %12, %%f56\n"
"ldd %13, %%f58\n"
"ldd %14, %%f60\n"
"ldd %15, %%f62\n"
:
: "m" (fctx->d[16]), "m" (fctx->d[17]), "m" (fctx->d[18]), "m" (fctx->d[19]),
"m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]),
"m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]),
"m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31])
);
fprs.dl = fprs.du = false;
fprs_write(fprs.value);
__asm__ volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr));
}
 
void fpu_enable(void)
{
pstate_reg_t pstate;
pstate.value = pstate_read();
pstate.pef = true;
pstate_write(pstate.value);
}
 
void fpu_disable(void)
{
pstate_reg_t pstate;
pstate.value = pstate_read();
pstate.pef = false;
pstate_write(pstate.value);
}
 
void fpu_init(void)
{
fpu_enable();
}
 
/** @}
*/
/trunk/kernel/arch/sparc64/src/asm.S
227,17 → 227,21
 
 
.macro WRITE_ALTERNATE_REGISTER reg, bit
rdpr %pstate, %g1 ! save PSTATE.PEF
wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
mov %o0, \reg
wrpr %g0, PSTATE_PRIV_BIT, %pstate
retl
wrpr %g0, PSTATE_PRIV_BIT, %pstate
wrpr %g1, 0, %pstate ! restore PSTATE.PEF
.endm
 
.macro READ_ALTERNATE_REGISTER reg, bit
rdpr %pstate, %g1 ! save PSTATE.PEF
wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
mov \reg, %o0
wrpr %g0, PSTATE_PRIV_BIT, %pstate
retl
wrpr %g0, PSTATE_PRIV_BIT, %pstate
wrpr %g1, 0, %pstate ! restore PSTATE.PEF
.endm
 
.global write_to_ag_g6
/trunk/kernel/arch/sparc64/src/trap/exception.c
37,6 → 37,7
#include <arch/interrupt.h>
#include <interrupt.h>
#include <arch/asm.h>
#include <arch/register.h>
#include <debug.h>
#include <typedefs.h>
#include <symtab.h>
81,6 → 82,27
panic("%s\n", __FUNCTION__);
}
 
/** Handle fp_disabled. (0x20) */
void fp_disabled(int n, istate_t *istate)
{
fprs_reg_t fprs;
fprs.value = fprs_read();
if (!fprs.fef) {
fprs.fef = true;
fprs_write(fprs.value);
return;
}
 
#ifdef CONFIG_FPU_LAZY
scheduler_fpu_lazy_request();
#else
fault_if_from_uspace(istate, "%s\n", __FUNCTION__);
dump_istate(istate);
panic("%s\n", __FUNCTION__);
#endif
}
 
/** Handle division_by_zero. (0x28) */
void division_by_zero(int n, istate_t *istate)
{
/trunk/kernel/arch/sparc64/src/trap/trap_table.S
82,10 → 82,16
privileged_opcode_tl0:
PREEMPTIBLE_HANDLER privileged_opcode
 
/* TT = 0x20, TL = 0, fb_disabled handler */
.org trap_table + TT_FP_DISABLED*ENTRY_SIZE
.global fb_disabled_tl0
fp_disabled_tl0:
PREEMPTIBLE_HANDLER fp_disabled
 
/* TT = 0x24, TL = 0, clean_window handler */
.org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE
.global clean_window_handler_tl0
clean_window_handler_tl0:
.global clean_window_tl0
clean_window_tl0:
CLEAN_WINDOW_HANDLER
 
/* TT = 0x28, TL = 0, division_by_zero */
489,8 → 495,8
 
/* TT = 0x24, TL > 0, clean_window handler */
.org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE
.global clean_window_handler_tl1
clean_window_handler_tl1:
.global clean_window_tl1
clean_window_tl1:
CLEAN_WINDOW_HANDLER
 
/* TT = 0x28, TL > 0, division_by_zero */
688,7 → 694,7
stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC]
wrpr %g0, 0, %tl
wrpr %g0, PSTATE_PRIV_BIT, %pstate
wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate
SAVE_GLOBALS
/*
705,6 → 711,7
.endif
 
RESTORE_GLOBALS
rdpr %pstate, %l1 ! we must preserve the PEF bit
wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
wrpr %g0, 1, %tl
716,6 → 723,15
ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3
 
/*
* Copy PSTATE.PEF to the in-register copy of TSTATE.
*/
and %l1, PSTATE_PEF_BIT, %l1
sllx %l1, TSTATE_PSTATE_SHIFT, %l1
sethi %hi(TSTATE_PEF_BIT), %g4
andn %g1, %g4, %g1
or %g1, %l1, %g1
 
/*
* Restore TSTATE, TPC and TNPC from saved copies.
*/
wrpr %g1, 0, %tstate
722,6 → 738,7
wrpr %g2, 0, %tpc
wrpr %g3, 0, %tnpc
 
 
/*
* If OTHERWIN is zero, then all the userspace windows have been
* spilled to kernel memory (i.e. register window buffer). Moreover,
/trunk/kernel/arch/sparc64/src/dummy.s
29,19 → 29,11
.text
 
.global cpu_sleep
.global fpu_context_restore
.global fpu_context_save
.global fpu_enable
.global fpu_init
.global sys_tls_set
 
.global dummy
 
cpu_sleep:
fpu_context_restore:
fpu_context_save:
fpu_enable:
fpu_init:
sys_tls_set:
 
dummy:
/trunk/kernel/arch/ia64/include/arch.h
26,14 → 26,14
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup ia64
/** @addtogroup ia64
* @{
*/
/** @file
*/
 
#ifndef __ia64_ARCH_H__
#define __ia64_ARCH_H__
#ifndef KERN_ia64_ARCH_H_
#define KERN_ia64_ARCH_H_
 
#define LOADED_PROG_STACK_PAGES_NO 2
 
41,6 → 41,5
 
#endif
 
/** @}
/** @}
*/
 
/trunk/kernel/arch/ia64/src/interrupt.c
157,26 → 157,26
char *desc = "";
 
switch (istate->cr_isr.ge_code) {
case GE_ILLEGALOP:
case GE_ILLEGALOP:
desc = "Illegal Operation fault";
break;
case GE_PRIVOP:
case GE_PRIVOP:
desc = "Privileged Operation fault";
break;
case GE_PRIVREG:
case GE_PRIVREG:
desc = "Privileged Register fault";
break;
case GE_RESREGFLD:
case GE_RESREGFLD:
desc = "Reserved Register/Field fault";
break;
case GE_DISBLDISTRAN:
case GE_DISBLDISTRAN:
desc = "Disabled Instruction Set Transition fault";
break;
case GE_ILLEGALDEP:
case GE_ILLEGALDEP:
desc = "Illegal Dependency fault";
break;
default:
desc = "unknown";
default:
desc = "unknown";
break;
}
 
186,8 → 186,6
panic("General Exception (%s)\n", desc);
}
 
void fpu_enable(void);
 
void disabled_fp_register(uint64_t vector, istate_t *istate)
{
#ifdef CONFIG_FPU_LAZY
205,7 → 203,6
}
 
 
 
/** Handle syscall. */
int break_instruction(uint64_t vector, istate_t *istate)
{
242,27 → 239,28
srlz_d();
 
switch(ivr.vector) {
case INTERRUPT_TIMER:
case INTERRUPT_TIMER:
it_interrupt();
break;
case INTERRUPT_SPURIOUS:
break;
case INTERRUPT_SPURIOUS:
printf("cpu%d: spurious interrupt\n", CPU->id);
break;
default:
default:
panic("\nUnhandled External Interrupt Vector %d\n", ivr.vector);
break;
}
}
 
void virtual_interrupt(uint64_t irq,void *param)
void virtual_interrupt(uint64_t irq, void *param)
{
switch(irq) {
case IRQ_KBD:
if(kbd_uspace) ipc_irq_send_notif(irq);
break;
default:
panic("\nUnhandled Virtual Interrupt request %d\n", irq);
case IRQ_KBD:
if (kbd_uspace)
ipc_irq_send_notif(irq);
break;
default:
panic("\nUnhandled Virtual Interrupt request %d\n", irq);
break;
}
}
 
269,8 → 267,8
/* Reregister irq to be IPC-ready */
void irq_ipc_bind_arch(unative_t irq)
{
if(irq==IRQ_KBD) {
kbd_uspace=1;
if(irq == IRQ_KBD) {
kbd_uspace = 1;
return;
}
return;
280,4 → 278,3
 
/** @}
*/
 
/trunk/kernel/arch/ppc32/include/arch.h
32,8 → 32,8
/** @file
*/
 
#ifndef __ppc32_ARCH_H__
#define __ppc32_ARCH_H__
#ifndef KERN_ppc32_ARCH_H_
#define KERN_ppc32_ARCH_H_
 
#include <arch/drivers/cuda.h>
 
/trunk/kernel/arch/amd64/include/arch.h
26,17 → 26,16
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup amd64
/** @addtogroup amd64
* @{
*/
/** @file
*/
 
#ifndef __amd64_ARCH_H__
#define __amd64_ARCH_H__
#ifndef KERN_amd64_ARCH_H_
#define KERN_amd64_ARCH_H_
 
#endif
 
/** @}
/** @}
*/
 
/trunk/kernel/arch/ppc64/include/arch.h
26,17 → 26,16
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup ppc64
/** @addtogroup ppc64
* @{
*/
/** @file
*/
 
#ifndef __ppc64_ARCH_H__
#define __ppc64_ARCH_H__
#ifndef KERN_ppc64_ARCH_H_
#define KERN_ppc64_ARCH_H_
 
#endif
 
/** @}
/** @}
*/
 
/trunk/kernel/arch/mips32/include/arch.h
32,8 → 32,8
/** @file
*/
 
#ifndef __mips32_ARCH_H__
#define __mips32_ARCH_H__
#ifndef KERN_mips32_ARCH_H_
#define KERN_mips32_ARCH_H_
 
#endif
 
/trunk/kernel/arch/mips32/src/fpu_context.c
26,7 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup mips32
/** @addtogroup mips32
* @{
*/
/** @file
57,6 → 57,5
/* TODO: Zero all registers */
}
 
/** @}
/** @}
*/
 
/trunk/kernel/arch/ia32/include/arch.h
26,17 → 26,16
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup ia32
/** @addtogroup ia32
* @{
*/
/** @file
*/
 
#ifndef __ia32_ARCH_H__
#define __ia32_ARCH_H__
#ifndef KERN_ia32_ARCH_H_
#define KERN_ia32_ARCH_H_
 
#endif
 
/** @}
/** @}
*/