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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /trunk/kernel/arch @ 3133

  → /trunk/kernel/arch @ 3134

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 3133 → Rev 3134

/trunk/kernel/arch/sparc64/include/barrier.h
57,10 → 57,8
#define write_barrier() \
asm volatile ("membar #StoreStore\n" ::: "memory")
static inline void flush(uintptr_t addr)
{
asm volatile ("flush %0\n" :: "r" (addr) : "memory");
}
#define flush(a) \
asm volatile ("flush %0\n" :: "r" ((a)) : "memory")
/** Flush Instruction Memory instruction. */
static inline void flush_blind(void)
90,6 → 88,15
flush((a)); \
}
#define FLUSH_INVAL_MIN 4
#define smc_coherence_block(a, l) \
{ \
unsigned long i; \
write_barrier(); \
for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \
flush((void *)(a) + i); \
}
#endif
/** @}

/trunk/kernel/arch/ia64/include/barrier.h
62,6 → 62,16
srlz_i(); \
}
#define FC_INVAL_MIN 32
#define smc_coherence_block(a, l) \
{ \
unsigned long i; \
for (i = 0; i < (l); i += FC_INVAL_MIN) \
fc_i((void *)(a) + i); \
sync_i(); \
srlz_i(); \
}
#endif
/** @}

/trunk/kernel/arch/arm32/include/barrier.h
47,6 → 47,7
#define write_barrier() asm volatile ("" ::: "memory")
#define smc_coherence(a)
#define smc_coherence_block(a, l)
#endif

/trunk/kernel/arch/ppc32/include/barrier.h
43,6 → 43,7
#define write_barrier() asm volatile ("eieio" ::: "memory")
#define smc_coherence(a)
#define smc_coherence_block(a, l)
#endif

/trunk/kernel/arch/ppc64/include/barrier.h
43,6 → 43,7
#define write_barrier() asm volatile ("eieio" ::: "memory")
#define smc_coherence(a)
#define smc_coherence_block(a, l)
#endif

/trunk/kernel/arch/mips32/include/barrier.h
46,6 → 46,7
#define write_barrier() asm volatile ("" ::: "memory")
#define smc_coherence(a)
#define smc_coherence_block(a, l)
#endif

/trunk/kernel/arch/ia32/include/barrier.h
91,6 → 91,7
* sufficient for them to drain to the D-cache).
*/
#define smc_coherence(a) write_barrier()
#define smc_coherence_block(a, l) write_barrier()
#endif