42,6 → 42,7 |
#include <arch/mm/tlb.h> |
#include <arch/mm/mmu.h> |
#include <arch/mm/tte.h> |
#include <arch/trap/regwin.h> |
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#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 |
#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 |
50,10 → 51,11 |
#define FAST_MMU_HANDLER_SIZE 128 |
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#ifdef __ASM__ |
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.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER |
/* |
* First, try to refill TLB from TSB. |
*/ |
! |
! First, try to refill TLB from TSB. |
! |
! TODO |
|
wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
74,7 → 76,7 |
* |
* Note that branch-delay slots are used in order to save space. |
*/ |
0: |
|
mov VA_DMMU_TAG_ACCESS, %g1 |
ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN |
set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 |
84,28 → 86,61 |
bz 0f ! page address is zero |
|
or %g3, (TTE_CP|TTE_P|TTE_W), %g2 ! 8K pages are the default (encoded as 0) |
set 1, %g3 |
sllx %g3, TTE_V_SHIFT, %g3 |
or %g2, %g3, %g2 |
mov 1, %g3 |
sllx %g3, TTE_V_SHIFT, %g3 |
or %g2, %g3, %g2 |
stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page |
retry |
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/* |
* Third, catch and handle special cases when the trap is caused by |
* some register window trap handler. |
* the userspace register window spill or fill handler. In case |
* one of these two traps caused this trap, we just lower the trap |
* level and service the DTLB miss. In the end, we restart |
* the offending SAVE or RESTORE. |
*/ |
0: |
! TODO |
HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL |
|
0: |
wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |
.endm |
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.macro FAST_DATA_ACCESS_PROTECTION_HANDLER |
/* |
* First, try to refill TLB from TSB. |
*/ |
! TODO |
|
/* |
* The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. |
*/ |
HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL |
|
wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
PREEMPTIBLE_HANDLER fast_data_access_protection |
.endm |
|
/* |
* Macro used to lower TL when a MMU trap is caused by |
* the userspace register window spill or fill handler. |
*/ |
.macro HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL |
rdpr %tl, %g1 |
dec %g1 |
brz %g1, 0f ! if TL was 1, skip |
nop |
wrpr %g1, 0, %tl ! TL-- |
rdpr %tt, %g2 |
cmp %g2, TT_SPILL_1_NORMAL |
be 0f ! trap from spill_1_normal |
cmp %g2, TT_FILL_1_NORMAL |
be 0f ! trap from fill_1_normal |
inc %g1 |
wrpr %g1, 0, %tl ! another trap, TL++ |
0: |
.endm |
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#endif /* __ASM__ */ |
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#endif |